xulie5.map.rpt

本设计是一个序列检测器

; Analysis & Synthesis Source Files Read                                                                                                                             ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                             ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+
; xulie5.bdf                       ; yes             ; User Block Diagram/Schematic File  ; D:/Quartus/xulie5/xulie5.bdf                                             ;
; 74161.tdf                        ; yes             ; Megafunction                       ; d:/program files/quartus7.1/quartus/libraries/others/maxplus2/74161.tdf  ;
; aglobal.inc                      ; yes             ; Megafunction                       ; d:/program files/quartus7.1/quartus/libraries/megafunctions/aglobal.inc  ;
; f74161.bdf                       ; yes             ; Megafunction                       ; d:/program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 5       ;
; Total combinational functions     ; 5       ;
;     -- Total 4-input functions    ; 1       ;
;     -- Total 3-input functions    ; 0       ;
;     -- Total 2-input functions    ; 0       ;
;     -- Total 1-input functions    ; 2       ;
;     -- Total 0-input functions    ; 2       ;
; Total registers                   ; 4       ;
; Total logic cells in carry chains ; 4       ;
; I/O pins                          ; 2       ;
; Maximum fan-out node              ; CLK     ;
; Maximum fan-out                   ; 4       ;
; Total fan-out                     ; 14      ;
; Average fan-out                   ; 2.00    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                              ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name           ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------+--------------+
; |xulie5                    ; 5 (1)       ; 4            ; 0           ; 2    ; 1 (1)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; 0 (0)      ; |xulie5                       ; work         ;
;    |74161:inst|            ; 4 (0)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; 0 (0)      ; |xulie5|74161:inst            ; work         ;
;       |f74161:sub|         ; 4 (4)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; 0 (0)      ; |xulie5|74161:inst|f74161:sub ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: 74161:inst ;
+------------------------+--------+-----------------------+
; Parameter Name         ; Value  ; Type                  ;
+------------------------+--------+-----------------------+
; DEVICE_FAMILY          ; ACEX1K ; Untyped               ;
; AUTO_CARRY_CHAINS      ; ON     ; AUTO_CARRY            ;
; IGNORE_CARRY_BUFFERS   ; OFF    ; IGNORE_CARRY          ;
; AUTO_CASCADE_CHAINS    ; ON     ; AUTO_CASCADE          ;
; IGNORE_CASCADE_BUFFERS ; OFF    ; IGNORE_CASCADE        ;
+------------------------+--------+-----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Nov 14 08:13:12 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off xulie5 -c xulie5
Info: Found 1 design units, including 1 entities, in source file xulie5.bdf
    Info: Found entity 1: xulie5
Info: Elaborating entity "xulie5" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file ../../program files/quartus7.1/quartus/libraries/others/maxplus2/74161.tdf
    Info: Found entity 1: 74161
Info: Elaborating entity "74161" for hierarchy "74161:inst"
Info: Elaborated megafunction instantiation "74161:inst"
Info: Found 1 design units, including 1 entities, in source file ../../program files/quartus7.1/quartus/libraries/others/maxplus2/f74161.bdf
    Info: Found entity 1: f74161
Info: Elaborating entity "f74161" for hierarchy "74161:inst|f74161:sub"
Info: Elaborated megafunction instantiation "74161:inst|f74161:sub", which is child of megafunction instantiation "74161:inst"
Info: Converted 1 single input CARRY primitives to CARRY_SUM primitives
Info: Implemented 7 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 5 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 138 megabytes of memory during processing
    Info: Processing ended: Wed Nov 14 08:13:14 2007
    Info: Elapsed time: 00:00:02