xulie5.tan.rpt

来自「本设计是一个序列检测器」· RPT 代码 · 共 167 行 · 第 1/2 页

+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|9   ; 74161:inst|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 2.200 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|9   ; 74161:inst|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 2.000 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|9   ; 74161:inst|f74161:sub|87  ; CLK        ; CLK      ; None                        ; None                      ; 1.800 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|9   ; 74161:inst|f74161:sub|9   ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|87  ; 74161:inst|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|110 ; 74161:inst|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 1.200 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|99  ; 74161:inst|f74161:sub|110 ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|87  ; 74161:inst|f74161:sub|87  ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|87  ; 74161:inst|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; 74161:inst|f74161:sub|99  ; 74161:inst|f74161:sub|99  ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
+-------+------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+---------------------------+----+------------+
; Slack ; Required tco ; Actual tco ; From                      ; To ; From Clock ;
+-------+--------------+------------+---------------------------+----+------------+
; N/A   ; None         ; 15.000 ns  ; 74161:inst|f74161:sub|110 ; co ; CLK        ;
; N/A   ; None         ; 14.800 ns  ; 74161:inst|f74161:sub|87  ; co ; CLK        ;
; N/A   ; None         ; 14.700 ns  ; 74161:inst|f74161:sub|9   ; co ; CLK        ;
; N/A   ; None         ; 14.500 ns  ; 74161:inst|f74161:sub|99  ; co ; CLK        ;
+-------+--------------+------------+---------------------------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Nov 14 08:13:35 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off xulie5 -c xulie5
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 200.0 MHz between source register "74161:inst|f74161:sub|9" and destination register "74161:inst|f74161:sub|110"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.200 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_L2; Fanout = 3; REG Node = '74161:inst|f74161:sub|9'
            Info: 2: + IC(0.200 ns) + CELL(0.700 ns) = 0.900 ns; Loc. = LC2_L2; Fanout = 2; COMB Node = '74161:inst|f74161:sub|81'
            Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.100 ns; Loc. = LC3_L2; Fanout = 2; COMB Node = '74161:inst|f74161:sub|85'
            Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 1.300 ns; Loc. = LC4_L2; Fanout = 1; COMB Node = '74161:inst|f74161:sub|95'
            Info: 5: + IC(0.000 ns) + CELL(0.900 ns) = 2.200 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst|f74161:sub|110'
            Info: Total cell delay = 2.000 ns ( 90.91 % )
            Info: Total interconnect delay = 0.200 ns ( 9.09 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst|f74161:sub|110'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
            Info: - Longest clock path from clock "CLK" to source register is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_L2; Fanout = 3; REG Node = '74161:inst|f74161:sub|9'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "CLK" to destination pin "co" through register "74161:inst|f74161:sub|110" is 15.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst|f74161:sub|110'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_L2; Fanout = 2; REG Node = '74161:inst|f74161:sub|110'
        Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC6_L2; Fanout = 1; COMB Node = 'inst16~118'
        Info: 3: + IC(1.100 ns) + CELL(8.500 ns) = 12.000 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'co'
        Info: Total cell delay = 10.700 ns ( 89.17 % )
        Info: Total interconnect delay = 1.300 ns ( 10.83 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Wed Nov 14 08:13:36 2007
    Info: Elapsed time: 00:00:01