chk.vhd

来自「本设计是一个序列检测器」· VHDL 代码 · 共 55 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  ENTITY CHK IS
    PORT (CLK,CLR: IN STD_LOGIC;
           DIN:IN STD_LOGIC;
            F: OUT STD_LOGIC);
  END CHK;
 ARCHITECTURE behav  OF CHK IS
 
  TYPE STATES IS (ST0, ST1, ST2, ST3, ST4);
  SIGNAL CURRENT_STATE,NEXT_STATE: STATES;
  
  BEGIN
P1:PROCESS(CLR,CLK)
 BEGIN
  IF CLR='1'THEN CURRENT_STATE<=ST0;
  ELSIF CLK'EVENT AND CLK='1' THEN
 CURRENT_STATE<=NEXT_STATE;
 END IF ;
END PROCESS P1;
P2:PROCESS(CURRENT_STATE,DIN)
    BEGIN
      CASE CURRENT_STATE IS
      WHEN ST0 => F<='0';
          IF DIN='1' THEN NEXT_STATE<=ST1;
                     ELSE NEXT_STATE<=ST0; 
          END IF;
      WHEN ST1=> F<='0';
                IF DIN='1' THEN NEXT_STATE<=ST2;
                    ELSE NEXT_STATE<=ST0;
                      
                 END IF;
      WHEN ST2=> F <='0';
            IF DIN='1' THEN NEXT_STATE<=ST2;
                   ELSE NEXT_STATE<=ST3;
                  
                 END IF;
      WHEN ST3=>  F<='0';
            IF DIN='1' THEN NEXT_STATE<=ST4;
                   ELSE NEXT_STATE<=ST0;
                  
                 END IF;   
      WHEN ST4=> F<='0';
           IF DIN='1' THEN NEXT_STATE<=ST2;
                   ELSE NEXT_STATE<=ST0;F<='1';
                  END IF;
      
     END CASE;
   END PROCESS p2;
END behav;