prev_cmp_chk.tan.qmsg

来自「本设计是一个序列检测器」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 5 -1 0 } } { "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register CURRENT_STATE.st0 CURRENT_STATE.st2 200.0 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 200.0 MHz between source register \"CURRENT_STATE.st0\" and destination register \"CURRENT_STATE.st2\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CURRENT_STATE.st0 1 REG LC5_E30 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_E30; Fanout = 1; REG Node = 'CURRENT_STATE.st0'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CURRENT_STATE.st0 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 1.400 ns CURRENT_STATE.st2 2 REG LC4_E30 2 " "Info: 2: + IC(0.200 ns) + CELL(1.200 ns) = 1.400 ns; Loc. = LC4_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st2'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CURRENT_STATE.st0 CURRENT_STATE.st2 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 85.71 % ) " "Info: Total cell delay = 1.200 ns ( 85.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 14.29 % ) " "Info: Total interconnect delay = 0.200 ns ( 14.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CURRENT_STATE.st0 CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CURRENT_STATE.st0 CURRENT_STATE.st2 } { 0.000ns 0.200ns } { 0.000ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns CURRENT_STATE.st2 2 REG LC4_E30 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st2'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK CURRENT_STATE.st2 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st2 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns CURRENT_STATE.st0 2 REG LC5_E30 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_E30; Fanout = 1; REG Node = 'CURRENT_STATE.st0'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK CURRENT_STATE.st0 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st0 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st2 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st0 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CURRENT_STATE.st0 CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { CURRENT_STATE.st0 CURRENT_STATE.st2 } { 0.000ns 0.200ns } { 0.000ns 1.200ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st2 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st0 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { CURRENT_STATE.st2 } {  } {  } "" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "CURRENT_STATE.st2 DaIN CLK 2.500 ns register " "Info: tsu for register \"CURRENT_STATE.st2\" (data pin = \"DaIN\", clock pin = \"CLK\") is 2.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest pin register " "Info: + Longest pin to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DaIN 1 PIN PIN_182 5 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 5; PIN Node = 'DaIN'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DaIN } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.300 ns) 3.700 ns CURRENT_STATE.st2 2 REG LC4_E30 2 " "Info: 2: + IC(1.900 ns) + CELL(1.300 ns) = 3.700 ns; Loc. = LC4_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st2'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { DaIN CURRENT_STATE.st2 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns ( 48.65 % ) " "Info: Total cell delay = 1.800 ns ( 48.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 51.35 % ) " "Info: Total interconnect delay = 1.900 ns ( 51.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { DaIN CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.700 ns" { DaIN DaIN~out CURRENT_STATE.st2 } { 0.000ns 0.000ns 1.900ns } { 0.000ns 0.500ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns CURRENT_STATE.st2 2 REG LC4_E30 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_E30; Fanout = 2; REG Node = 'CURRENT_STATE.st2'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK CURRENT_STATE.st2 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st2 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { DaIN CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "3.700 ns" { DaIN DaIN~out CURRENT_STATE.st2 } { 0.000ns 0.000ns 1.900ns } { 0.000ns 0.500ns 1.300ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st2 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st2 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK F CURRENT_STATE.st4 15.100 ns register " "Info: tco from clock \"CLK\" to destination pin \"F\" through register \"CURRENT_STATE.st4\" is 15.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns CURRENT_STATE.st4 2 REG LC2_E30 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_E30; Fanout = 1; REG Node = 'CURRENT_STATE.st4'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK CURRENT_STATE.st4 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st4 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.100 ns + Longest register pin " "Info: + Longest register to pin delay is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CURRENT_STATE.st4 1 REG LC2_E30 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E30; Fanout = 1; REG Node = 'CURRENT_STATE.st4'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CURRENT_STATE.st4 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 1.900 ns F~2 2 COMB LC1_E30 1 " "Info: 2: + IC(0.200 ns) + CELL(1.700 ns) = 1.900 ns; Loc. = LC1_E30; Fanout = 1; COMB Node = 'F~2'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CURRENT_STATE.st4 F~2 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(8.500 ns) 12.100 ns F 3 PIN PIN_73 0 " "Info: 3: + IC(1.700 ns) + CELL(8.500 ns) = 12.100 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'F'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { F~2 F } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.200 ns ( 84.30 % ) " "Info: Total cell delay = 10.200 ns ( 84.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 15.70 % ) " "Info: Total interconnect delay = 1.900 ns ( 15.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "12.100 ns" { CURRENT_STATE.st4 F~2 F } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "12.100 ns" { CURRENT_STATE.st4 F~2 F } { 0.000ns 0.200ns 1.700ns } { 0.000ns 1.700ns 8.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK CURRENT_STATE.st4 } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out CURRENT_STATE.st4 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "12.100 ns" { CURRENT_STATE.st4 F~2 F } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "12.100 ns" { CURRENT_STATE.st4 F~2 F } { 0.000ns 0.200ns 1.700ns } { 0.000ns 1.700ns 8.500ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "DaIN F 14.500 ns Longest " "Info: Longest tpd from source pin \"DaIN\" to destination pin \"F\" is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DaIN 1 PIN PIN_182 5 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 5; PIN Node = 'DaIN'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DaIN } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 4.300 ns F~2 2 COMB LC1_E30 1 " "Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 4.300 ns; Loc. = LC1_E30; Fanout = 1; COMB Node = 'F~2'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { DaIN F~2 } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(8.500 ns) 14.500 ns F 3 PIN PIN_73 0 " "Info: 3: + IC(1.700 ns) + CELL(8.500 ns) = 14.500 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'F'" {  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { F~2 F } "NODE_NAME" } } { "CHK.vhd" "" { Text "D:/Quartus/CHK/CHK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.900 ns ( 75.17 % ) " "Info: Total cell delay = 10.900 ns ( 75.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 24.83 % ) " "Info: Total interconnect delay = 3.600 ns ( 24.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { DaIN F~2 F } "NODE_NAME" } } { "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus7.1/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { DaIN DaIN~out F~2 F } { 0.000ns 0.000ns 1.900ns 1.700ns } { 0.000ns 0.500ns 1.900ns 8.500ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}