jianche.vhd

来自「本设计是一个序列检测器」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JIANCHE IS
PORT(clk,clr:IN STD_LOGIC;
     CQ,CO:OUT STD_LOGIC );
END ENTITY JIANCHE;
ARCHITECTURE behav OF JIANCHE IS
COMPONENT xulie5 IS
 PORT(CLK:IN STD_LOGIC;
      CI:OUT STD_LOGIC);
END COMPONENT;
COMPONENT CHK IS
 PORT( CLK,CLR,DaIN:IN STD_LOGIC;
      F:OUT STD_LOGIC);
 END COMPONENT;
SIGNAL A:STD_LOGIC;
BEGIN 
u1:xulie5 PORT MAP(CLK=>clk,CI=>A);
u2:CHK PORT MAP(CLK=>clk,CLR=>clr,DaIN=>A,F=>CO);
CQ<=A;
END ARCHITECTURE behav;