or2a.vhd

本设计是一个序列检测器

LIBRARY IEEE;
USE STD_LOGIC_1164.ALL;
ENTITY OR2A IS
PORT(a,b:IN STD_LOGIC;
     c OUT STD_LOGIC);
END ENTITY OR2A;
ARCHITECTURE beahv OF OR2A IS
BEGIN
    b<=1
   c<=a and b;
END ARCHITECTURE behav;