pwm.vhd

用VHDL编写的PWM控制程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pwm IS
	PORT(clr:IN	STD_LOGIC;
		clk:IN STD_LOGIC;
		txd,txd2,rxd_l,rxd2_l:IN	STD_LOGIC;
		rxd,rxd2,txd_l,txd2_l:OUT   STD_LOGIC;
		Ch_PWMA,Ch_PWMB: out STD_LOGIC_VECTOR(9 downto 0);
		data: in STD_LOGIC_VECTOR(7 downto 0); --
		address: in std_logic_vector(4 downto 0);
		out_ena,out_enb:	in std_logic;
		
		nwe: in std_logic
		);
END		pwm;

ARCHITECTURE	zas	OF	pwm	IS
	signal  ChTimer1a,ChTimer1d: std_logic_vector(7 downto 0);	
	signal  ChTimer2a,ChTimer2d: std_logic_vector(7 downto 0);	
	signal  ChTimer3a,ChTimer3d: std_logic_vector(7 downto 0);	
	signal  ChTimer4a,ChTimer4d: std_logic_vector(7 downto 0);	
	signal  ChTimer5a,ChTimer5d: std_logic_vector(7 downto 0);	
	signal  ChTimer6a,ChTimer6d: std_logic_vector(7 downto 0);	
	signal  ChTimer7a,ChTimer7d: std_logic_vector(7 downto 0);	
	signal  ChTimer8a,ChTimer8d: std_logic_vector(7 downto 0);	
	signal  ChTimer9a,ChTimer9d: std_logic_vector(7 downto 0);	
	signal  ChTimer10a,ChTimer10d: std_logic_vector(7 downto 0);	

	signal  ChTmp1: std_logic_vector(8 downto 0);	
	signal  ChTmp2: std_logic_vector(8 downto 0);	
	signal  ChTmp3: std_logic_vector(8 downto 0);	
	signal  ChTmp4: std_logic_vector(8 downto 0);	
	signal  ChTmp5: std_logic_vector(8 downto 0);	
	signal  ChTmp6: std_logic_vector(8 downto 0);	
	signal  ChTmp7: std_logic_vector(8 downto 0);	
	signal  ChTmp8: std_logic_vector(8 downto 0);	
	signal  ChTmp9: std_logic_vector(8 downto 0);	
	signal  ChTmp10: std_logic_vector(8 downto 0);	
	
	signal  Timer :std_logic_vector(9 downto 0);	
BEGIN				
	
	--串口要通过光藕，所以要反相一下
	txd_l <=  txd2;
	txd2_l <= txd;
	rxd <=  rxd2_l;
	rxd2 <= rxd_l;

	--单片机写操作
	PROCESS(clk,nwe,data,address,clr)
	BEGIN			
		if(nwe'event and nwe ='1')then -- nwe的上升沿
			case address is
				when "00000"=> ChTimer1a<=data(7 downto 0);
				when "00001"=> ChTimer1d<=data(7 downto 0);
				when "00010"=> ChTimer2a<=data(7 downto 0);
				when "00011"=> ChTimer2d<=data(7 downto 0);
				when "00100"=> ChTimer3a<=data(7 downto 0);
				when "00101"=> ChTimer3d<=data(7 downto 0);
				when "00110"=> ChTimer4a<=data(7 downto 0);
				when "00111"=> ChTimer4d<=data(7 downto 0);
				when "01000"=> ChTimer5a<=data(7 downto 0);
				when "01001"=> ChTimer5d<=data(7 downto 0);
				when "01010"=> ChTimer6a<=data(7 downto 0);
				when "01011"=> ChTimer6d<=data(7 downto 0);
				when "01100"=> ChTimer7a<=data(7 downto 0);
				when "01101"=> ChTimer7d<=data(7 downto 0);
				when "01110"=> ChTimer8a<=data(7 downto 0);
				when "01111"=> ChTimer8d<=data(7 downto 0);
				when "10000"=> ChTimer9a<=data(7 downto 0);
				when "10001"=> ChTimer9d<=data(7 downto 0);
				when "10010"=> ChTimer10a<=data(7 downto 0);
				when "10011"=> ChTimer10d<=data(7 downto 0);
				when others => null;
			end case;
		end if;
		
		--系统复位后，将寄存器之0
--		if(clr='0') then
--			ChTimer1 <= "0000000000"; 
--			ChTimer2 <= "0000000000"; 
--			ChTimer3 <= "0000000000"; 
--			ChTimer4 <= "0000000000";
--			ChTimer5 <= "0000000000";
--			ChTimer6 <= "0000000000"; 
--			ChTimer7 <= "0000000000"; 
--			ChTimer8 <= "0000000000"; 
--			ChTimer9 <= "0000000000"; 
--			ChTimer10 <= "0000000000"; 
--		end if;
	END	PROCESS;
	---debug <= Chtmp1(7 downto 0);
--以下用于调试，设定值自动递增，正常时不使用。
--	process(clr,Timer(28))
--	begin		
--		if(Timer(28)'event and Timer(28)='1') then  -- dclk
--			ChTimer1 <= ChTimer1 +'1'; 		
--		end if;			
--	end process;
	
	process(clk,clr)
	begin
	if(clk'event and clk='1') then  -- dclk
		Timer<=Timer+'1';
		if((Timer(9 downto 0)="0000000000")or(Timer(9 downto 0)="0100000000")or(Timer(9 downto 0)="1000000000")) then  -- 初始化处置
			ChTmp1<='0'&ChTimer1a;
			ChTmp2<='0'&ChTimer2a;
			ChTmp3<='0'&ChTimer3a;
			ChTmp4<='0'&ChTimer4a;
			ChTmp5<='0'&ChTimer5a;
			ChTmp6<='0'&ChTimer6a;
			ChTmp7<='0'&ChTimer7a;
			ChTmp8<='0'&ChTimer8a;
			ChTmp9<='0'&ChTimer9a;
			ChTmp10<='0'&ChTimer10a;
		elsif(Timer(9 downto 0)="1100000000") then  -- 初始化处置
			ChTmp1<='0'&ChTimer1d;
			ChTmp2<='0'&ChTimer2d;
			ChTmp3<='0'&ChTimer3d;
			ChTmp4<='0'&ChTimer4d;
			ChTmp5<='0'&ChTimer5d;
			ChTmp6<='0'&ChTimer6d;
			ChTmp7<='0'&ChTimer7d;
			ChTmp8<='0'&ChTimer8d;
			ChTmp9<='0'&ChTimer9d;
			ChTmp10<='0'&ChTimer10d;
		else
			ChTmp1<=ChTmp1+'1';
			ChTmp2<=ChTmp2+'1';
			ChTmp3<=ChTmp3+'1';
			ChTmp4<=ChTmp4+'1';
			ChTmp5<=ChTmp5+'1';
			ChTmp6<=ChTmp6+'1';
			ChTmp7<=ChTmp7+'1';
			ChTmp8<=ChTmp8+'1';
			ChTmp9<=ChTmp9+'1';
			ChTmp10<=ChTmp10+'1';
		end if;
	end if;
	
	end process;
				Ch_PWMA(0) <= ChTmp1(8) and out_ena;
				Ch_PWMA(1) <= ChTmp2(8) and out_ena;
				Ch_PWMA(2) <= ChTmp3(8) and out_ena;
				Ch_PWMA(3) <= ChTmp4(8) and out_ena;
				Ch_PWMA(4) <= ChTmp5(8) and out_ena;
				Ch_PWMA(5) <= ChTmp6(8) and out_ena;
				Ch_PWMA(6) <= ChTmp7(8) and out_ena;
				Ch_PWMA(7) <= ChTmp8(8) and out_ena;
				Ch_PWMA(8) <= ChTmp9(8) and out_ena;
				Ch_PWMA(9) <= ChTmp10(8) and out_ena;
					
				Ch_PWMB(0) <= ChTmp1(8) and out_enb and (not out_ena);
				Ch_PWMB(1) <= ChTmp2(8) and out_enb and (not out_ena);
				Ch_PWMB(2) <= ChTmp3(8) and out_enb and (not out_ena);
				Ch_PWMB(3) <= ChTmp4(8) and out_enb and (not out_ena);
				Ch_PWMB(4) <= ChTmp5(8) and out_enb and (not out_ena);
				Ch_PWMB(5) <= ChTmp6(8) and out_enb and (not out_ena);
				Ch_PWMB(6) <= ChTmp7(8) and out_enb and (not out_ena);
				Ch_PWMB(7) <= ChTmp8(8) and out_enb and (not out_ena);
				Ch_PWMB(8) <= ChTmp9(8) and out_enb and (not out_ena);
				Ch_PWMB(9) <= ChTmp10(8) and out_enb and (not out_ena);
END	zas;