uart.vhd

用VHDL实现的一个uart控制器

LIBRARY IEEE;
use	IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_1164.ALL;

--实现一个FIFO控制器
--TXD 数据发送
--signal 

ENTITY UART IS 
	PORT(
		TXD:	OUT STD_LOGIC;
		RSTN:	IN STD_LOGIC;
		CLK:    IN STD_LOGIC;
		UART_BUSY: OUT STD_LOGIC;
		
		data: 	in std_logic_vector(7 downto 0);
--		debug_uart_res_tmp: out std_logic;		
--		debug_uart_data: 	out std_logic_vector(7 downto 0);
		data_en:	in std_logic
	);
END UART;

ARCHITECTURE UART_ARCH OF UART IS 
	SIGNAL uart_data:std_logic_vector(7 downto 0);
--	signal data_en:std_logic; 
	signal uart_clk:	std_logic;
	signal uart_res_tmp:	std_logic;
	signal uart_state: std_logic_vector (3 downto 0);
	signal uart_timer: std_logic_vector (9 downto 0);
--	signal buff0,buff1,buff2,buff3: std_logic_vector(31 downto 0); --用于数据缓冲
	
BEGIN
--	debug_uart_data <=uart_data;
--	debug_uart_res_tmp <= uart_res_tmp;
	
	process(rstn,uart_clk,uart_state)
	begin
		if(uart_clk'event and uart_clk='1') then
			case uart_state is 
				when "0000"=> if(uart_res_tmp='1') then
								 uart_state <= "0001";
							  else
								 txd <= '0';   --空闲
							  end if;
			    when "0001"=> txd <= '1';   --起始位
							  uart_state <= uart_state +'1';
				when "0010"=> txd <= not uart_data(0);
							  uart_state <= uart_state +'1';
				when "0011"=> txd <= not uart_data(1);
							  uart_state <= uart_state +'1';
				when "0100"=> txd <= not uart_data(2);
							  uart_state <= uart_state +'1';
				when "0101"=> txd <= not uart_data(3);
							  uart_state <= uart_state +'1';
				when "0110"=> txd <= not uart_data(4);
							  uart_state <= uart_state +'1';
				when "0111"=> txd <= not uart_data(5);
							  uart_state <= uart_state +'1';
				when "1000"=> txd <= not uart_data(6);
							  uart_state <= uart_state +'1';
				when "1001"=> txd <= not uart_data(7);
							  uart_state <= uart_state +'1';
				when "1010"=> txd <='0';    -- 停止位
							  uart_state <= "0000";  --置空闲
				when others=> uart_state <= "0000";							  
			end case;
			
		end if;
		
		if(rstn ='0') then
			txd <='0';
			uart_state <="0000";
		end if;
	end process;
	
-- 从33M时钟获取11.0592k的时钟
	-- 从33M时钟获取11.0592k的时钟
	process(rstn,clk,uart_timer)
	begin
		if(clk'event and clk='1') then
			uart_timer <= uart_timer +'1';
			
			if(uart_timer = "0010001111") then
			--if(uart_timer = "0000000001") then		
				uart_clk <='0';
			elsif(uart_timer="0100011110") then
			--elsif(uart_timer="0000000010") then			
				uart_clk <='1';
			elsif(uart_timer="0110101101") then
			--elsif(uart_timer="0000000011") then			
				uart_clk <='0';
			elsif(uart_timer="1000111101") then
			--elsif(uart_timer="0000000100") then			
				uart_clk <='1';
				uart_timer <="0000000000";
			end if;
			
		end if;
		
		if(rstn ='0') then
			uart_clk<='1';
			uart_timer<="0000000000";
		end if;				
	end process;
--	uart_clk <= clk;
	
	--根据data_en/uart_res 设置uart_res_tmp变量的值
	process(rstn,clk,data_en)
	begin
		if(clk'event and clk='1') then
			if(data_en ='0') then
				uart_res_tmp <='1';  --要求发送数据
				uart_busy <='0';
				uart_data <= data(7 downto 0);
			elsif(uart_state ="0000" and uart_res_tmp<='0') then
				uart_busy <='1';
			end if;
			if(uart_state/="0000") then
				uart_res_tmp <='0';
			end if;			
		end if;
		
		if(rstn ='0') then
			uart_res_tmp <='0';
			uart_data <=X"FF";
			uart_busy <='1';
		end if;
	end process;

END UART_ARCH;