tb_full_adder.vhd

来自「內含fulladder結構檔,電路檔,測試檔(testbench)以及執行檔(.」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pkg_Full_Adder.all;

entity tb_Full_Adder is
end;

architecture arc of tb_Full_Adder is
    signal in1, in2, carryin : std_logic;
    signal sum, carryout     : std_logic;
begin
    process
    begin
        in1 <= '0';  in2 <= '0';  carryin <= '0';  wait for 20 ns;
        in1 <= '0';  in2 <= '0';  carryin <= '1';  wait for 20 ns;
        in1 <= '0';  in2 <= '1';  carryin <= '0';  wait for 20 ns;
        in1 <= '0';  in2 <= '1';  carryin <= '1';  wait for 20 ns;
        in1 <= '1';  in2 <= '0';  carryin <= '0';  wait for 20 ns;
        in1 <= '1';  in2 <= '0';  carryin <= '1';  wait for 20 ns;
        in1 <= '1';  in2 <= '1';  carryin <= '0';  wait for 20 ns;
        in1 <= '1';  in2 <= '1';  carryin <= '1';  wait for 20 ns;
        assert   false
        report   "    End of Simulation"
        severity failure;
     end process;

     Full_Adder_Inst: Full_Adder port map
         ( in1       =>  in1,
           in2       =>  in2,
           carryin   =>  carryin,
           sum       =>  sum,
           carryout  =>  carryout
         );
end arc;