📄 disp.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity disp is
port ( clk3 :in std_logic;
bcdmo :in std_logic_vector(3 downto 0);
sel :out std_logic_vector(2 downto 1);
seg :out std_logic_vector(6 downto 0);
light :out std_logic_vector;
dot :out std_logic_vector);
end ;
architecture a of disp is
signal f,f1,f2 :std_logic_vector(3 downto 0);
signal segsig :std_logic_vector(6 downto 0);
signal selsig :std_logic_vector(2 downto 1);
signal numlet,l,dp :std_logic;
signal temp :integer range 0 to 10;
begin
p4:
process
begin
if(bcdmo="0001")then
f1<="0001";f2<="0000"; temp<=1; l<='0'; dp<='0';
elsif(bcdmo="0010")then
f1<="0101";f2<="0000"; temp<=5; l<='0'; dp<='0';
elsif(bcdmo="0011")then
f1<="0000";f2<="0001"; temp<=10; l<='0'; dp<='0';
elsif(bcdmo="0101")then
f2<="0000";
case temp is
when 1=>f1<="0000"; l<='1'; dp<='0';
when 5=>f1<="0100"; l<='1'; dp<='0';
when 10=>f1<="1001"; l<='1'; dp<='0';
when others=>f1<="0000"; l<='0'; dp<='1';
end case;
elsif(bcdmo="0110")then
f2<="0000";
case temp is
when 1=>f1<="0001"; l<='0'; dp<='1';
when 5=>f1<="0010"; l<='1'; dp<='0';
when 10=>f1<="0111"; l<='1'; dp<='0';
when others=>f1<="0000"; l<='0'; dp<='1';
end case;
elsif(bcdmo="0111")then
f2<="0000";
case temp is
when 1=>f1<="0001"; l<='0'; dp<='1';
when 5=>f1<="0101"; l<='0'; dp<='1';
when 10=>f1<="0011"; l<='1'; dp<='0';
when others=>f1<="0000"; l<='0'; dp<='1';
end case;
else
f2<="0000";f1<="0000"; l<='0'; dp<='0'; temp<=0;
end if;
end process p4;
p5:
process(clk3)
begin
if(clk3'event and clk3='1')then
if(numlet='0')then
f<=f1;selsig(2 downto 0)<="10";
else
f<=f2;selsig(2 downto 0)<="01";
end if;
numlet<=not numlet;
end if;
case f is
when "0000"=>segsig(6 downto 0)<="1111110";
when "0001"=>segsig(6 downto 0)<="0110000";
when "0010"=>segsig(6 downto 0)<="1101101";
when "0011"=>segsig(6 downto 0)<="1111001";
when "0100"=>segsig(6 downto 0)<="0110011";
when "0101"=>segsig(6 downto 0)<="1011011";
when "0110"=>segsig(6 downto 0)<="1011111";
when "0111"=>segsig(6 downto 0)<="1110000";
when "1001"=>segsig(6 downto 0)<="1111011";
when others=>segsig(6 downto 0)<="0000000";
end case;
end process p5;
sel<=selsig;
seg(6 downto 0)<=segsig(6 downto 0);
light<=1;
dot<=dp;
end;
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