📄 fenpin.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port ( clk :in std_logic;
clk1 :out std_logic;
clk2,clk3:out std_logic);
end;
architecture a of fenpin is
signal count:std_logic_vector(12 downto 0);
signal a,c :std_logic;
begin
p1:
process(clk)
begin
if(clk'event and clk='1')then
if(count="1001110001000")then
count<="0000000000000"; a<=not a;
else count<=count+1;
end if;
end if;
clk2<=a;
clk3<=a;
end process p1;
p2:
process(a)
begin
if(a'event and a='1')then
c<=not c;
end if;
clk1<=c;
end process;
end;
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