📄 keyin.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keyin is
port(clk1 :in std_logic;
col :in std_logic_vector(3 downto 0);
row :out std_logic_vector(3 downto 0);
bcdmin :out std_logic_vector(3 downto 0));
end;
architecture a of keyin is
signal line:std_logic_vector( 3 downto 0);
begin
p1:
process(clk1)
begin
if(line="0000")then line<="1000";
elsif(clk1'event and clk1='1')then
line (3 downto 0)<= line (2 downto 0)&line(3);
end if;
end process p1;
row(3)<=line(3);
row(2)<=line(2);
row(1)<=line(1);
row(0)<=line(0);
p2:
process
begin
if(line="0000"and col="10000") then bcdmin<="0001";
elsif(line="1000" and col="0100")then
bcdmin<="0010";
elsif(line="1000" and col="0010")then
bcdmin<="0011";
elsif(line="0100" and col="1000")then
bcdmin<="0101";
elsif(line="0100" and col="0100")then
bcdmin<="0110";
elsif(line="0100" and col="0010")then
bcdmin<="0111";
else bcdmin<="0000";
end if;
end process p2;
end;
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