songer.vhd

用VHDL编写的播放器

library ieee;
use ieee.std_logic_1164.all;

entity songer is
   port(clk12MHz: in std_logic;
        clk8Hz: in std_logic;
        code1: out integer range 0 to 15;
         high1: out std_logic;
         spkout: out std_logic);
end;

architecture one of songer is
   component notetabs
      port( clk: in std_logic;
           toneindex: out integer range 0 to 15);
   end component;
   component tonetaba
      port( index : in integer range 0 to 15;
             code : out integer range 0 to 15;
             high : out std_logic;
             tone : out integer range 0 to 16#7FF#);
   end component;
   component speakera
      port(clk : in std_logic;
           tone: in integer range 0 to 16#7FF#;
           spks: out std_logic);
   end component;
   
   signal tone: integer range 0 to 16#7FF#;
   signal toneindex: integer range 0 to 15;
 begin 
    u1: notetabs port map(clk=>clk8Hz,toneIndex=>toneIndex) ;
    u2: tonetaba port map(index=>toneindex,tone=>tone,
                          code=>code1,high=>high1);
    u3: speakera port map(clk=>clk12MHz,tone=>tone,spks=>spkout);
end;