ad0804.fit.qmsg

来自「对ad0804的控制工程」· QMSG 代码 · 共 49 行 · 第 1/4 页

{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.500 ns memory register " "Info: Estimated most critical path is memory to register delay of 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_c7p3:auto_generated\|altsyncram_ogq1:altsyncram1\|ram_block2a2~porta_address_reg11 1 MEM M4K_X11_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y8; Fanout = 1; MEM Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_c7p3:auto_generated\|altsyncram_ogq1:altsyncram1\|ram_block2a2~porta_address_reg11'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated|altsyncram_ogq1:altsyncram1|ram_block2a2~porta_address_reg11 } "NODE_NAME" } } { "db/altsyncram_ogq1.tdf" "" { Text "F:/72quartus/ADCONTRL0804/db/altsyncram_ogq1.tdf" 103 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.761 ns) 3.761 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_c7p3:auto_generated\|altsyncram_ogq1:altsyncram1\|q_a\[2\] 2 MEM M4K_X11_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X11_Y8; Fanout = 1; MEM Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_c7p3:auto_generated\|altsyncram_ogq1:altsyncram1\|q_a\[2\]'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "3.761 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated|altsyncram_ogq1:altsyncram1|ram_block2a2~porta_address_reg11 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated|altsyncram_ogq1:altsyncram1|q_a[2] } "NODE_NAME" } } { "db/altsyncram_ogq1.tdf" "" { Text "F:/72quartus/ADCONTRL0804/db/altsyncram_ogq1.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.981 ns) + CELL(0.650 ns) 6.392 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|_~1172 3 COMB LAB_X22_Y12 1 " "Info: 3: + IC(1.981 ns) + CELL(0.650 ns) = 6.392 ns; Loc. = LAB_X22_Y12; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|_~1172'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "2.631 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated|altsyncram_ogq1:altsyncram1|q_a[2] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~1172 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 532 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.500 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] 4 REG LAB_X22_Y12 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 6.500 ns; Loc. = LAB_X22_Y12; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\]'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~1172 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.519 ns ( 69.52 % ) " "Info: Total cell delay = 4.519 ns ( 69.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.981 ns ( 30.48 % ) " "Info: Total interconnect delay = 1.981 ns ( 30.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated|altsyncram_ogq1:altsyncram1|ram_block2a2~porta_address_reg11 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated|altsyncram_ogq1:altsyncram1|q_a[2] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~1172 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}