📄 zerojustv.v
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module zerojustv(clk,clear,Din,Dout,aorb);
input clk,clear;
input [7:0]Din;
output Dout,aorb;
parameter s80 =43'b000000000000_0000000000_0000000000_0000000000_1;
parameter s81 =43'b000000000000_0000000000_0000000000_0000000001_0;
parameter s82 =43'b000000000000_0000000000_0000000000_0000000010_0;
parameter s83 =43'b000000000000_0000000000_0000000000_0000000100_0;
parameter s84 =43'b000000000000_0000000000_0000000000_0000001000_0;
parameter s85 =43'b000000000000_0000000000_0000000000_0000010000_0;
parameter s90 =43'b000000000000_0000000000_0000000000_0000100000_0;
parameter s91 =43'b000000000000_0000000000_0000000000_0001000000_0;
parameter s92 =43'b000000000000_0000000000_0000000000_0010000000_0;
parameter s61 =43'b000000000000_0000000000_0000000000_0100000000_0;
parameter s62 =43'b000000000000_0000000000_0000000000_1000000000_0;
parameter s101=43'b000000000000_0000000000_0000000001_0000000000_0;
parameter s102=43'b000000000000_0000000000_0000000010_0000000000_0;
parameter s201=43'b000000000000_0000000000_0000000100_0000000000_0;
parameter s202=43'b000000000000_0000000000_0000001000_0000000000_0;
parameter s4 =43'b000000000000_0000000000_0000010000_0000000000_0;
parameter s5 =43'b000000000000_0000000000_0000100000_0000000000_0;
parameter s6 =43'b000000000000_0000000000_0001000000_0000000000_0;
parameter s671=43'b000000000000_0000000000_0010000000_0000000000_0;
parameter s672=43'b000000000000_0000000000_0100000000_0000000000_0;
parameter s673=43'b000000000000_0000000000_1000000000_0000000000_0;
parameter s674=43'b000000000000_0000000001_0000000000_0000000000_0;
parameter s675=43'b000000000000_0000000010_0000000000_0000000000_0;
parameter s676=43'b000000000000_0000000100_0000000000_0000000000_0;
parameter s677=43'b000000000000_0000001000_0000000000_0000000000_0;
parameter s678=43'b000000000000_0000010000_0000000000_0000000000_0;
parameter s7 =43'b000000000000_0000100000_0000000000_0000000000_0;
parameter s71 =43'b000000000000_0001000000_0000000000_0000000000_0;
parameter s0 =43'b000000000000_0010000000_0000000000_0000000000_0;
parameter s1 =43'b000000000000_0100000000_0000000000_0000000000_0;
parameter s2 =43'b000000000000_1000000000_0000000000_0000000000_0;
parameter s231=43'b000000000001_0000000000_0000000000_0000000000_0;
parameter s232=43'b000000000010_0000000000_0000000000_0000000000_0;
parameter s233=43'b000000000100_0000000000_0000000000_0000000000_0;
parameter s234=43'b000000001000_0000000000_0000000000_0000000000_0;
parameter s235=43'b000000010000_0000000000_0000000000_0000000000_0;
parameter s236=43'b000000100000_0000000000_0000000000_0000000000_0;
parameter s237=43'b000001000000_0000000000_0000000000_0000000000_0;
parameter s238=43'b000010000000_0000000000_0000000000_0000000000_0;
parameter s3 =43'b000100000000_0000000000_0000000000_0000000000_0;
parameter s31 =43'b001000000000_0000000000_0000000000_0000000000_0;
parameter s72 =43'b010000000000_0000000000_0000000000_0000000000_0; parameter s32 =43'b100000000000_0000000000_0000000000_0000000000_0;
reg[42:0] current_state,next_state;
always @(negedge clear or negedge clk) begin
if(!clear) begin
current_state<=s80;
end
else
current_state<=next_state;
end
reg Dout,aorb;
reg ini;
always @(posedge clk or negedge clear) begin
if(!clear) begin
Dout<=1'b0;
aorb<=1'b0;
ini<=1'b0;end
else
case(current_state)
s80: begin Dout<=1'b0;
aorb<=1'b1;
ini<=2'd0;
next_state<=s81;end
s81: begin Dout<=1'b0;
next_state<=s82;end
s82: begin Dout<=1'b0;
next_state<=s83;end
s83: begin Dout<=1'b0;
next_state<=s84;end
s84: begin Dout<=1'b0;
next_state<=s85;end
s85: begin Dout<=1'b0;
next_state<=s90;end
s90: if(Din[7]==0) next_state<=s91;//决定判断初始值正或负的方向
else next_state<=s61;
s91: if(Din[7]==0) next_state<=s92;
else next_state<=s101;
s92: if(Din[7]==0) begin next_state<=s4;ini<=1'b1; end//确定初始值为正
else next_state<=s61;
s61: if(Din[7]==1) next_state<=s62;
else next_state<=s201;
s62: if(Din[7]==1) begin next_state<=s0;ini<=1'b1; end//确定初始值为负
else next_state<=s61;
s101:if(Din[7]==1) next_state<=s102;
else next_state<=s90;
s102:if(Din[7]==1) begin next_state<=s0;ini<=1'b1; end //确定初始值为负
else next_state<=s90;
s201:if(Din[7]==0) next_state<=s202;
else next_state<=s90;
s202:if(Din[7]==0) begin next_state<=s4;ini<=1'b1; end//确定初始值为正
else next_state<=s90;
s4: begin
Dout<=1'b0;
aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s5;end
s5: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s6;end
s6: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s671;end
s671: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s672;end
s672: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s673;end
s673: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s674;end
s674: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s677;end
// s675: begin aorb<=1'b1;
// if(Din[7]==0) next_state<=s4;
// else next_state<=s676;end
// s676: begin aorb<=1'b1;
// if(Din[7]==0) next_state<=s4;
// else next_state<=s677;end
s677: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s678;end
s678: begin aorb<=1'b1;
if(Din[7]==0) next_state<=s4;
else next_state<=s7;end //确定由正值变为负值
s7: begin if(ini<=1'b0)
Dout<=1'b1;
else begin Dout<=1'b0; ini<=1'b0; end
aorb<=1'b0;
if(Din[7]==0) next_state<=s0;//启动负变正判别过程
else next_state<=s71; end
s71: begin
aorb<=1'b0;
Dout<=1'b0;
if(Din[7]==0) next_state<=s0;//启动负变正判别过程
else next_state<=s72; end
s72: begin
Dout<=1'b0;
aorb<=1'b0;
if(Din[7]==0) next_state<=s0;//启动负变正判别过程
else next_state<=s71; end
s0: begin
Dout<=1'b0;
aorb<=1'b0;
if(Din[7]==0) next_state<=s1;
else next_state<=s0; end
s1: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s2;
else next_state<=s0; end
s2: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s231;
else next_state<=s0; end
s231: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s232;
else next_state<=s0; end
s232: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s233;
else next_state<=s0; end
s233: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s234;
else next_state<=s0; end
s234: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s237;
else next_state<=s0; end
// s235: begin
// aorb<=1'b0;
// if(Din[7]==0) next_state<=s236;
// else next_state<=s0; end
// s236: begin
// aorb<=1'b0;
// if(Din[7]==0) next_state<=s237;
// else next_state<=s0; end
s237: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s238;
else next_state<=s0; end
s238: begin
aorb<=1'b0;
if(Din[7]==0) next_state<=s3;//确定由负值变为正值
else next_state<=s0; end
s3: begin
Dout<=1'b1;
aorb<=1'b1;
if(Din[7]==1) next_state<=s4;//启动正变负判别过程⌨️ 快捷键说明
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