stp2.stp

来自「用verilog写的对ad0809的控制」· STP 代码 · 共 147 行 · 第 1/4 页

          <wire name="EOC" tap_mode="classic" type="input pin"/>
          <wire name="OE" tap_mode="classic" type="output pin"/>
          <wire name="START" tap_mode="classic" type="output pin"/>
          <wire name="d1" tap_mode="classic" type="input pin"/>
          <wire name="d2" tap_mode="classic" type="input pin"/>
          <wire name="d3" tap_mode="classic" type="input pin"/>
          <wire name="d4" tap_mode="classic" type="input pin"/>
          <wire name="d5" tap_mode="classic" type="input pin"/>
          <wire name="d6" tap_mode="classic" type="input pin"/>
          <wire name="d7" tap_mode="classic" type="input pin"/>
          <wire name="d8" tap_mode="classic" type="input pin"/>
          <wire name="led1" tap_mode="classic" type="output pin"/>
          <wire name="led2" tap_mode="classic" type="output pin"/>
          <wire name="led3" tap_mode="classic" type="output pin"/>
          <wire name="led4" tap_mode="classic" type="output pin"/>
          <wire name="led5" tap_mode="classic" type="output pin"/>
          <wire name="led6" tap_mode="classic" type="output pin"/>
          <wire name="led7" tap_mode="classic" type="output pin"/>
          <wire name="led8" tap_mode="classic" type="output pin"/>
          <wire name="rst_n" tap_mode="classic" type="input pin"/>
          <wire name="scl" tap_mode="classic" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="scl"/>
          <net is_signal_inverted="no" name="ALE"/>
          <net is_signal_inverted="no" name="EOC"/>
          <net is_signal_inverted="no" name="OE"/>
          <net is_signal_inverted="no" name="START"/>
          <net is_signal_inverted="no" name="d1"/>
          <net is_signal_inverted="no" name="d2"/>
          <net is_signal_inverted="no" name="d3"/>
          <net is_signal_inverted="no" name="d4"/>
          <net is_signal_inverted="no" name="d5"/>
          <net is_signal_inverted="no" name="d6"/>
          <net is_signal_inverted="no" name="d7"/>