prev_cmp_byte_crc.map.qmsg

来自「字节型CRC校验 采用verilog语言设计」· QMSG 代码 · 共 8 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 30 21:30:38 2008 " "Info: Processing started: Thu Oct 30 21:30:38 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off byte_crc -c byte_crc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off byte_crc -c byte_crc" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "byte_crc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file byte_crc.v" { { "Info" "ISGN_ENTITY_NAME" "1 byte_crc " "Info: Found entity 1: byte_crc" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_UNDEF_TOP_PORT" "prevcrc byte_crc.v(4) " "Error (10206): Verilog HDL Module Declaration error at byte_crc.v(4): top module port \"prevcrc\" is not found in the port list" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 4 0 0 } }  } 0 10206 "Verilog HDL Module Declaration error at %2!s!: top module port \"%1!s!\" is not found in the port list" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_ASSIGNMENT_TO_INPUT" "prevcrc byte_crc.v(15) " "Error (10231): Verilog HDL error at byte_crc.v(15): value cannot be assigned to input \"prevcrc\"" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 15 0 0 } }  } 0 10231 "Verilog HDL error at %2!s!: value cannot be assigned to input \"%1!s!\"" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Error: Peak virtual memory: 155 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Oct 30 21:30:40 2008 " "Error: Processing ended: Thu Oct 30 21:30:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}