prev_cmp_byte_crc.tan.qmsg

来自「字节型CRC校验 采用verilog语言设计」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "ITDB_TSU_RESULT" "buf_crc\[7\] prevcrc\[10\] sig 7.557 ns register " "Info: tsu for register \"buf_crc\[7\]\" (data pin = \"prevcrc\[10\]\", clock pin = \"sig\") is 7.557 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.770 ns + Longest pin register " "Info: + Longest pin to register delay is 10.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.924 ns) 0.924 ns prevcrc\[10\] 1 PIN PIN_AB10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.924 ns) = 0.924 ns; Loc. = PIN_AB10; Fanout = 2; PIN Node = 'prevcrc\[10\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { prevcrc[10] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.354 ns) + CELL(0.650 ns) 9.928 ns Mux1~52 2 COMB LCCOMB_X40_Y30_N20 2 " "Info: 2: + IC(8.354 ns) + CELL(0.650 ns) = 9.928 ns; Loc. = LCCOMB_X40_Y30_N20; Fanout = 2; COMB Node = 'Mux1~52'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.004 ns" { prevcrc[10] Mux1~52 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.370 ns) 10.662 ns Mux8~48 3 COMB LCCOMB_X40_Y30_N28 1 " "Info: 3: + IC(0.364 ns) + CELL(0.370 ns) = 10.662 ns; Loc. = LCCOMB_X40_Y30_N28; Fanout = 1; COMB Node = 'Mux8~48'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { Mux1~52 Mux8~48 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 10.770 ns buf_crc\[7\] 4 REG LCFF_X40_Y30_N29 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 10.770 ns; Loc. = LCFF_X40_Y30_N29; Fanout = 1; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Mux8~48 buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.052 ns ( 19.05 % ) " "Info: Total cell delay = 2.052 ns ( 19.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.718 ns ( 80.95 % ) " "Info: Total interconnect delay = 8.718 ns ( 80.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.770 ns" { prevcrc[10] Mux1~52 Mux8~48 buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "10.770 ns" { prevcrc[10] {} prevcrc[10]~combout {} Mux1~52 {} Mux8~48 {} buf_crc[7] {} } { 0.000ns 0.000ns 8.354ns 0.364ns 0.000ns } { 0.000ns 0.924ns 0.650ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 3.173 ns - Shortest register " "Info: - Shortest clock path from clock \"sig\" to destination register is 3.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.666 ns) 3.173 ns buf_crc\[7\] 3 REG LCFF_X40_Y30_N29 1 " "Info: 3: + IC(1.178 ns) + CELL(0.666 ns) = 3.173 ns; Loc. = LCFF_X40_Y30_N29; Fanout = 1; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.844 ns" { sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.34 % ) " "Info: Total cell delay = 1.756 ns ( 55.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.417 ns ( 44.66 % ) " "Info: Total interconnect delay = 1.417 ns ( 44.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.173 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.178ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.770 ns" { prevcrc[10] Mux1~52 Mux8~48 buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "10.770 ns" { prevcrc[10] {} prevcrc[10]~combout {} Mux1~52 {} Mux8~48 {} buf_crc[7] {} } { 0.000ns 0.000ns 8.354ns 0.364ns 0.000ns } { 0.000ns 0.924ns 0.650ns 0.370ns 0.108ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.173 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.178ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sig crc\[2\] buf_crc\[14\] 12.675 ns register " "Info: tco from clock \"sig\" to destination pin \"crc\[2\]\" through register \"buf_crc\[14\]\" is 12.675 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig source 3.173 ns + Longest register " "Info: + Longest clock path from clock \"sig\" to source register is 3.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.666 ns) 3.173 ns buf_crc\[14\] 3 REG LCFF_X40_Y30_N21 2 " "Info: 3: + IC(1.178 ns) + CELL(0.666 ns) = 3.173 ns; Loc. = LCFF_X40_Y30_N21; Fanout = 2; REG Node = 'buf_crc\[14\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.844 ns" { sig~clkctrl buf_crc[14] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.34 % ) " "Info: Total cell delay = 1.756 ns ( 55.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.417 ns ( 44.66 % ) " "Info: Total interconnect delay = 1.417 ns ( 44.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { sig sig~clkctrl buf_crc[14] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.173 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[14] {} } { 0.000ns 0.000ns 0.239ns 1.178ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.198 ns + Longest register pin " "Info: + Longest register to pin delay is 9.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buf_crc\[14\] 1 REG LCFF_X40_Y30_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y30_N21; Fanout = 2; REG Node = 'buf_crc\[14\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { buf_crc[14] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.982 ns) + CELL(3.216 ns) 9.198 ns crc\[2\] 2 PIN PIN_AA12 0 " "Info: 2: + IC(5.982 ns) + CELL(3.216 ns) = 9.198 ns; Loc. = PIN_AA12; Fanout = 0; PIN Node = 'crc\[2\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.198 ns" { buf_crc[14] crc[2] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.216 ns ( 34.96 % ) " "Info: Total cell delay = 3.216 ns ( 34.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.982 ns ( 65.04 % ) " "Info: Total interconnect delay = 5.982 ns ( 65.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.198 ns" { buf_crc[14] crc[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "9.198 ns" { buf_crc[14] {} crc[2] {} } { 0.000ns 5.982ns } { 0.000ns 3.216ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { sig sig~clkctrl buf_crc[14] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.173 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[14] {} } { 0.000ns 0.000ns 0.239ns 1.178ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.198 ns" { buf_crc[14] crc[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "9.198 ns" { buf_crc[14] {} crc[2] {} } { 0.000ns 5.982ns } { 0.000ns 3.216ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "g\[3\]~reg0 rst sig -1.853 ns register " "Info: th for register \"g\[3\]~reg0\" (data pin = \"rst\", clock pin = \"sig\") is -1.853 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 3.193 ns + Longest register " "Info: + Longest clock path from clock \"sig\" to destination register is 3.193 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.666 ns) 3.193 ns g\[3\]~reg0 3 REG LCFF_X61_Y32_N11 1 " "Info: 3: + IC(1.198 ns) + CELL(0.666 ns) = 3.193 ns; Loc. = LCFF_X61_Y32_N11; Fanout = 1; REG Node = 'g\[3\]~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.864 ns" { sig~clkctrl g[3]~reg0 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.00 % ) " "Info: Total cell delay = 1.756 ns ( 55.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.437 ns ( 45.00 % ) " "Info: Total interconnect delay = 1.437 ns ( 45.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.193 ns" { sig sig~clkctrl g[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.193 ns" { sig {} sig~combout {} sig~clkctrl {} g[3]~reg0 {} } { 0.000ns 0.000ns 0.239ns 1.198ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.352 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns rst 1 PIN PIN_M2 9 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M2; Fanout = 9; PIN Node = 'rst'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.407 ns) + CELL(0.855 ns) 5.352 ns g\[3\]~reg0 2 REG LCFF_X61_Y32_N11 1 " "Info: 2: + IC(3.407 ns) + CELL(0.855 ns) = 5.352 ns; Loc. = LCFF_X61_Y32_N11; Fanout = 1; REG Node = 'g\[3\]~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.262 ns" { rst g[3]~reg0 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.945 ns ( 36.34 % ) " "Info: Total cell delay = 1.945 ns ( 36.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.407 ns ( 63.66 % ) " "Info: Total interconnect delay = 3.407 ns ( 63.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.352 ns" { rst g[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.352 ns" { rst {} rst~combout {} g[3]~reg0 {} } { 0.000ns 0.000ns 3.407ns } { 0.000ns 1.090ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.193 ns" { sig sig~clkctrl g[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.193 ns" { sig {} sig~combout {} sig~clkctrl {} g[3]~reg0 {} } { 0.000ns 0.000ns 0.239ns 1.198ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.352 ns" { rst g[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.352 ns" { rst {} rst~combout {} g[3]~reg0 {} } { 0.000ns 0.000ns 3.407ns } { 0.000ns 1.090ns 0.855ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Peak virtual memory: 126 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 30 21:19:15 2008 " "Info: Processing ended: Thu Oct 30 21:19:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}