byte_crc.tan.qmsg

来自「字节型CRC校验 采用verilog语言设计」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sig register register buf_crc\[7\] buf_crc\[15\] 340.02 MHz Internal " "Info: Clock \"sig\" Internal fmax is restricted to 340.02 MHz between source register \"buf_crc\[7\]\" and destination register \"buf_crc\[15\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.825 ns + Longest register register " "Info: + Longest register to register delay is 1.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buf_crc\[7\] 1 REG LCFF_X43_Y33_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.624 ns) 1.717 ns buf_crc~15 2 COMB LCCOMB_X43_Y33_N14 1 " "Info: 2: + IC(1.093 ns) + CELL(0.624 ns) = 1.717 ns; Loc. = LCCOMB_X43_Y33_N14; Fanout = 1; COMB Node = 'buf_crc~15'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.717 ns" { buf_crc[7] buf_crc~15 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.825 ns buf_crc\[15\] 3 REG LCFF_X43_Y33_N15 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.825 ns; Loc. = LCFF_X43_Y33_N15; Fanout = 4; REG Node = 'buf_crc\[15\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { buf_crc~15 buf_crc[15] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.732 ns ( 40.11 % ) " "Info: Total cell delay = 0.732 ns ( 40.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.093 ns ( 59.89 % ) " "Info: Total interconnect delay = 1.093 ns ( 59.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.825 ns" { buf_crc[7] buf_crc~15 buf_crc[15] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.825 ns" { buf_crc[7] {} buf_crc~15 {} buf_crc[15] {} } { 0.000ns 1.093ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 3.189 ns + Shortest register " "Info: + Shortest clock path from clock \"sig\" to destination register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.666 ns) 3.189 ns buf_crc\[15\] 3 REG LCFF_X43_Y33_N15 4 " "Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N15; Fanout = 4; REG Node = 'buf_crc\[15\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.860 ns" { sig~clkctrl buf_crc[15] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.06 % ) " "Info: Total cell delay = 1.756 ns ( 55.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.433 ns ( 44.94 % ) " "Info: Total interconnect delay = 1.433 ns ( 44.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[15] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[15] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig source 3.189 ns - Longest register " "Info: - Longest clock path from clock \"sig\" to source register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.666 ns) 3.189 ns buf_crc\[7\] 3 REG LCFF_X43_Y33_N31 2 " "Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.860 ns" { sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.06 % ) " "Info: Total cell delay = 1.756 ns ( 55.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.433 ns ( 44.94 % ) " "Info: Total interconnect delay = 1.433 ns ( 44.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[15] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[15] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.825 ns" { buf_crc[7] buf_crc~15 buf_crc[15] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.825 ns" { buf_crc[7] {} buf_crc~15 {} buf_crc[15] {} } { 0.000ns 1.093ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[15] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[15] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { buf_crc[15] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { buf_crc[15] {} } {  } {  } "" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "buf_crc\[7\] pdata\[6\] sig 5.984 ns register " "Info: tsu for register \"buf_crc\[7\]\" (data pin = \"pdata\[6\]\", clock pin = \"sig\") is 5.984 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.213 ns + Longest pin register " "Info: + Longest pin to register delay is 9.213 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.915 ns) 0.915 ns pdata\[6\] 1 PIN PIN_G5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.915 ns) = 0.915 ns; Loc. = PIN_G5; Fanout = 3; PIN Node = 'pdata\[6\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { pdata[6] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.970 ns) + CELL(0.650 ns) 8.535 ns Mux13~84 2 COMB LCCOMB_X43_Y33_N28 3 " "Info: 2: + IC(6.970 ns) + CELL(0.650 ns) = 8.535 ns; Loc. = LCCOMB_X43_Y33_N28; Fanout = 3; COMB Node = 'Mux13~84'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.620 ns" { pdata[6] Mux13~84 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.206 ns) 9.105 ns Mux8~46 3 COMB LCCOMB_X43_Y33_N30 1 " "Info: 3: + IC(0.364 ns) + CELL(0.206 ns) = 9.105 ns; Loc. = LCCOMB_X43_Y33_N30; Fanout = 1; COMB Node = 'Mux8~46'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.570 ns" { Mux13~84 Mux8~46 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.213 ns buf_crc\[7\] 4 REG LCFF_X43_Y33_N31 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 9.213 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Mux8~46 buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.879 ns ( 20.40 % ) " "Info: Total cell delay = 1.879 ns ( 20.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.334 ns ( 79.60 % ) " "Info: Total interconnect delay = 7.334 ns ( 79.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.213 ns" { pdata[6] Mux13~84 Mux8~46 buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "9.213 ns" { pdata[6] {} pdata[6]~combout {} Mux13~84 {} Mux8~46 {} buf_crc[7] {} } { 0.000ns 0.000ns 6.970ns 0.364ns 0.000ns } { 0.000ns 0.915ns 0.650ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 3.189 ns - Shortest register " "Info: - Shortest clock path from clock \"sig\" to destination register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.666 ns) 3.189 ns buf_crc\[7\] 3 REG LCFF_X43_Y33_N31 2 " "Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.860 ns" { sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.06 % ) " "Info: Total cell delay = 1.756 ns ( 55.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.433 ns ( 44.94 % ) " "Info: Total interconnect delay = 1.433 ns ( 44.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.213 ns" { pdata[6] Mux13~84 Mux8~46 buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "9.213 ns" { pdata[6] {} pdata[6]~combout {} Mux13~84 {} Mux8~46 {} buf_crc[7] {} } { 0.000ns 0.000ns 6.970ns 0.364ns 0.000ns } { 0.000ns 0.915ns 0.650ns 0.206ns 0.108ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sig crc\[7\] buf_crc\[7\] 11.831 ns register " "Info: tco from clock \"sig\" to destination pin \"crc\[7\]\" through register \"buf_crc\[7\]\" is 11.831 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig source 3.189 ns + Longest register " "Info: + Longest clock path from clock \"sig\" to source register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.666 ns) 3.189 ns buf_crc\[7\] 3 REG LCFF_X43_Y33_N31 2 " "Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.860 ns" { sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.06 % ) " "Info: Total cell delay = 1.756 ns ( 55.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.433 ns ( 44.94 % ) " "Info: Total interconnect delay = 1.433 ns ( 44.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.338 ns + Longest register pin " "Info: + Longest register to pin delay is 8.338 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buf_crc\[7\] 1 REG LCFF_X43_Y33_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { buf_crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.312 ns) + CELL(3.026 ns) 8.338 ns crc\[7\] 2 PIN PIN_H6 0 " "Info: 2: + IC(5.312 ns) + CELL(3.026 ns) = 8.338 ns; Loc. = PIN_H6; Fanout = 0; PIN Node = 'crc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.338 ns" { buf_crc[7] crc[7] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.026 ns ( 36.29 % ) " "Info: Total cell delay = 3.026 ns ( 36.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.312 ns ( 63.71 % ) " "Info: Total interconnect delay = 5.312 ns ( 63.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.338 ns" { buf_crc[7] crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "8.338 ns" { buf_crc[7] {} crc[7] {} } { 0.000ns 5.312ns } { 0.000ns 3.026ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[7] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.338 ns" { buf_crc[7] crc[7] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "8.338 ns" { buf_crc[7] {} crc[7] {} } { 0.000ns 5.312ns } { 0.000ns 3.026ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "buf_crc\[1\] pdata\[5\] sig -3.675 ns register " "Info: th for register \"buf_crc\[1\]\" (data pin = \"pdata\[5\]\", clock pin = \"sig\") is -3.675 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 3.189 ns + Longest register " "Info: + Longest clock path from clock \"sig\" to destination register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns sig 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns sig~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { sig sig~clkctrl } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.666 ns) 3.189 ns buf_crc\[1\] 3 REG LCFF_X43_Y33_N19 2 " "Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N19; Fanout = 2; REG Node = 'buf_crc\[1\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.860 ns" { sig~clkctrl buf_crc[1] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.06 % ) " "Info: Total cell delay = 1.756 ns ( 55.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.433 ns ( 44.94 % ) " "Info: Total interconnect delay = 1.433 ns ( 44.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[1] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[1] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.170 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.904 ns) 0.904 ns pdata\[5\] 1 PIN PIN_E14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_E14; Fanout = 3; PIN Node = 'pdata\[5\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { pdata[5] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.788 ns) + CELL(0.370 ns) 7.062 ns Mux14~84 2 COMB LCCOMB_X43_Y33_N18 3 " "Info: 2: + IC(5.788 ns) + CELL(0.370 ns) = 7.062 ns; Loc. = LCCOMB_X43_Y33_N18; Fanout = 3; COMB Node = 'Mux14~84'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.158 ns" { pdata[5] Mux14~84 } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.170 ns buf_crc\[1\] 3 REG LCFF_X43_Y33_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.170 ns; Loc. = LCFF_X43_Y33_N19; Fanout = 2; REG Node = 'buf_crc\[1\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Mux14~84 buf_crc[1] } "NODE_NAME" } } { "byte_crc.v" "" { Text "D:/altera/work2/byte_crc/byte_crc.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.382 ns ( 19.27 % ) " "Info: Total cell delay = 1.382 ns ( 19.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.788 ns ( 80.73 % ) " "Info: Total interconnect delay = 5.788 ns ( 80.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.170 ns" { pdata[5] Mux14~84 buf_crc[1] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "7.170 ns" { pdata[5] {} pdata[5]~combout {} Mux14~84 {} buf_crc[1] {} } { 0.000ns 0.000ns 5.788ns 0.000ns } { 0.000ns 0.904ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { sig sig~clkctrl buf_crc[1] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { sig {} sig~combout {} sig~clkctrl {} buf_crc[1] {} } { 0.000ns 0.000ns 0.239ns 1.194ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.170 ns" { pdata[5] Mux14~84 buf_crc[1] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "7.170 ns" { pdata[5] {} pdata[5]~combout {} Mux14~84 {} buf_crc[1] {} } { 0.000ns 0.000ns 5.788ns 0.000ns } { 0.000ns 0.904ns 0.370ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}