byte_crc.v

字节型CRC校验 采用verilog语言设计

module byte_crc(rst, sig, pdata, /*prevcrc,*/ crc);
    input rst, sig;
	input [ 7 : 0] pdata;
	//input [15 : 0] prevcrc;
	reg [15 : 0] prevcrc_buf;
	output [15 : 0] crc;
	reg [15 : 0] buf_crc;	
	reg [15:0] crcTable[0 : 255];
	reg [15:0] crcTable_buf;
	reg [7 : 0] i;
	reg [8 : 0] j;
	assign crc = buf_crc;	
	wire [15 : 0] prevcrc;
		
	assign prevcrc = crc;
	always @(negedge sig or negedge rst)
	begin
	if(~rst)	
		begin
		buf_crc = 16'h0000;
		
		for(j = 0; j < 256; j = j+ 1)
			begin
			crcTable_buf = 0;
			for(i = 8 'h80; i != 0; i = i >> 1)
				begin
				if((crcTable_buf & 16 'h8000) != 0)
					begin
					crcTable_buf = crcTable_buf << 1;
					crcTable_buf = crcTable_buf ^ 17 'h11021;
					end
				else               
					crcTable_buf = crcTable_buf << 1;
				if((j & i) != 0)                
					crcTable_buf = crcTable_buf ^ 17'h11021;
				end
			crcTable [j] = crcTable_buf;
			end	
		end
	else
		begin
			buf_crc = prevcrc >> 8;
			prevcrc_buf = prevcrc << 8;			
			buf_crc = prevcrc_buf ^ crcTable[buf_crc ^ pdata];			
		end 
	end
			
endmodule