byte_crc.tan.rpt

字节型CRC校验 采用verilog语言设计

; N/A           ; None        ; -4.258 ns ; pdata[5] ; buf_crc[13] ; sig      ;
; N/A           ; None        ; -4.450 ns ; pdata[0] ; buf_crc[0]  ; sig      ;
; N/A           ; None        ; -4.491 ns ; pdata[7] ; buf_crc[8]  ; sig      ;
; N/A           ; None        ; -4.493 ns ; pdata[7] ; buf_crc[15] ; sig      ;
; N/A           ; None        ; -4.501 ns ; pdata[3] ; buf_crc[3]  ; sig      ;
; N/A           ; None        ; -4.586 ns ; pdata[2] ; buf_crc[2]  ; sig      ;
; N/A           ; None        ; -4.651 ns ; pdata[4] ; buf_crc[5]  ; sig      ;
; N/A           ; None        ; -4.654 ns ; pdata[4] ; buf_crc[12] ; sig      ;
; N/A           ; None        ; -4.779 ns ; pdata[1] ; buf_crc[6]  ; sig      ;
; N/A           ; None        ; -4.779 ns ; pdata[1] ; buf_crc[13] ; sig      ;
; N/A           ; None        ; -5.089 ns ; pdata[3] ; buf_crc[8]  ; sig      ;
; N/A           ; None        ; -5.091 ns ; pdata[3] ; buf_crc[15] ; sig      ;
; N/A           ; None        ; -5.142 ns ; pdata[6] ; buf_crc[6]  ; sig      ;
; N/A           ; None        ; -5.146 ns ; pdata[6] ; buf_crc[11] ; sig      ;
; N/A           ; None        ; -5.148 ns ; pdata[6] ; buf_crc[2]  ; sig      ;
; N/A           ; None        ; -5.156 ns ; pdata[2] ; buf_crc[7]  ; sig      ;
; N/A           ; None        ; -5.156 ns ; pdata[2] ; buf_crc[14] ; sig      ;
; N/A           ; None        ; -5.204 ns ; pdata[0] ; buf_crc[5]  ; sig      ;
; N/A           ; None        ; -5.207 ns ; pdata[0] ; buf_crc[12] ; sig      ;
; N/A           ; None        ; -5.718 ns ; pdata[6] ; buf_crc[7]  ; sig      ;
; N/A           ; None        ; -5.718 ns ; pdata[6] ; buf_crc[14] ; sig      ;
+---------------+-------------+-----------+----------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Oct 30 21:32:00 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off byte_crc -c byte_crc --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "sig" is an undefined clock
Info: Clock "sig" Internal fmax is restricted to 340.02 MHz between source register "buf_crc[7]" and destination register "buf_crc[15]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.825 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc[7]'
            Info: 2: + IC(1.093 ns) + CELL(0.624 ns) = 1.717 ns; Loc. = LCCOMB_X43_Y33_N14; Fanout = 1; COMB Node = 'buf_crc~15'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.825 ns; Loc. = LCFF_X43_Y33_N15; Fanout = 4; REG Node = 'buf_crc[15]'
            Info: Total cell delay = 0.732 ns ( 40.11 % )
            Info: Total interconnect delay = 1.093 ns ( 59.89 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "sig" to destination register is 3.189 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'
                Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'
                Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N15; Fanout = 4; REG Node = 'buf_crc[15]'
                Info: Total cell delay = 1.756 ns ( 55.06 % )
                Info: Total interconnect delay = 1.433 ns ( 44.94 % )
            Info: - Longest clock path from clock "sig" to source register is 3.189 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'
                Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'
                Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc[7]'
                Info: Total cell delay = 1.756 ns ( 55.06 % )
                Info: Total interconnect delay = 1.433 ns ( 44.94 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "buf_crc[7]" (data pin = "pdata[6]", clock pin = "sig") is 5.984 ns
    Info: + Longest pin to register delay is 9.213 ns
        Info: 1: + IC(0.000 ns) + CELL(0.915 ns) = 0.915 ns; Loc. = PIN_G5; Fanout = 3; PIN Node = 'pdata[6]'
        Info: 2: + IC(6.970 ns) + CELL(0.650 ns) = 8.535 ns; Loc. = LCCOMB_X43_Y33_N28; Fanout = 3; COMB Node = 'Mux13~84'
        Info: 3: + IC(0.364 ns) + CELL(0.206 ns) = 9.105 ns; Loc. = LCCOMB_X43_Y33_N30; Fanout = 1; COMB Node = 'Mux8~46'
        Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 9.213 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc[7]'
        Info: Total cell delay = 1.879 ns ( 20.40 % )
        Info: Total interconnect delay = 7.334 ns ( 79.60 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "sig" to destination register is 3.189 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'
        Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'
        Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc[7]'
        Info: Total cell delay = 1.756 ns ( 55.06 % )
        Info: Total interconnect delay = 1.433 ns ( 44.94 % )
Info: tco from clock "sig" to destination pin "crc[7]" through register "buf_crc[7]" is 11.831 ns
    Info: + Longest clock path from clock "sig" to source register is 3.189 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'
        Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'
        Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc[7]'
        Info: Total cell delay = 1.756 ns ( 55.06 % )
        Info: Total interconnect delay = 1.433 ns ( 44.94 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 8.338 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X43_Y33_N31; Fanout = 2; REG Node = 'buf_crc[7]'
        Info: 2: + IC(5.312 ns) + CELL(3.026 ns) = 8.338 ns; Loc. = PIN_H6; Fanout = 0; PIN Node = 'crc[7]'
        Info: Total cell delay = 3.026 ns ( 36.29 % )
        Info: Total interconnect delay = 5.312 ns ( 63.71 % )
Info: th for register "buf_crc[1]" (data pin = "pdata[5]", clock pin = "sig") is -3.675 ns
    Info: + Longest clock path from clock "sig" to destination register is 3.189 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sig'
        Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'sig~clkctrl'
        Info: 3: + IC(1.194 ns) + CELL(0.666 ns) = 3.189 ns; Loc. = LCFF_X43_Y33_N19; Fanout = 2; REG Node = 'buf_crc[1]'
        Info: Total cell delay = 1.756 ns ( 55.06 % )
        Info: Total interconnect delay = 1.433 ns ( 44.94 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.170 ns
        Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_E14; Fanout = 3; PIN Node = 'pdata[5]'
        Info: 2: + IC(5.788 ns) + CELL(0.370 ns) = 7.062 ns; Loc. = LCCOMB_X43_Y33_N18; Fanout = 3; COMB Node = 'Mux14~84'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.170 ns; Loc. = LCFF_X43_Y33_N19; Fanout = 2; REG Node = 'buf_crc[1]'
        Info: Total cell delay = 1.382 ns ( 19.27 % )
        Info: Total interconnect delay = 5.788 ns ( 80.73 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Thu Oct 30 21:32:02 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01