alu.v

来自「关于FPGA的CPU的设计」· Verilog 代码 · 共 32 行

` timescale 1ns/1ns
  module cpu_alu(alu_out,zero,opcode,data_in,acc,clk);
  input [4:0] opcode;
  input [7:0] acc,data_in;
  input clk;
  output [7:0] alu_out;
  output zero;
  reg[7:0] alu_out;
  parameter z_delay=1.5,alu_delay=4.5;
  always @(posedge clk)
   begin
      case(opcode)
        5'b00000:#alu_delay alu_out=acc;
        5'b00001:#alu_delay alu_out=data_in+acc;
        5'b00010:#alu_delay alu_out=data_in&acc;
        5'b00011:#alu_delay alu_out=data_in^acc;
       // 3'b101:#alu_delay alu_out=data_in;
        //3'b110:#alu_delay alu_out=acc;
        //3'b111:#alu_delay alu_out=acc;
     default:
      // begin
        //  $display("unkown opcode");
          //#alu_delay alu_out=16'bx;
       //end
       begin
           #alu_delay alu_out=8'bz;
       end
    endcase
 end
assign #z_delay zero=(acc==0)?1:0;
endmodule