proj.tan.qmsg

基于ep1c6的vhdl的lcd控制程序实例

{ "Info" "ITDB_FULL_TCO_RESULT" "clk LCD_D\[3\] lcd:inst\|counter\[5\] 39.212 ns register " "Info: tco from clock \"clk\" to destination pin \"LCD_D\[3\]\" through register \"lcd:inst\|counter\[5\]\" is 39.212 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 22.283 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 22.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns div16:inst2\|count\[3\] 2 REG LC_X8_Y10_N6 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 17; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.680 ns" { clk div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns lcd:inst\|clkcnt\[6\] 3 REG LC_X8_Y12_N1 4 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X8_Y12_N1; Fanout = 4; REG Node = 'lcd:inst\|clkcnt\[6\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.444 ns" { div16:inst2|count[3] lcd:inst|clkcnt[6] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(0.590 ns) 9.463 ns lcd:inst\|reduce_nor~378 4 COMB LC_X9_Y11_N2 1 " "Info: 4: + IC(1.280 ns) + CELL(0.590 ns) = 9.463 ns; Loc. = LC_X9_Y11_N2; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~378'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.870 ns" { lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.590 ns) 10.509 ns lcd:inst\|reduce_nor~380 5 COMB LC_X9_Y11_N7 7 " "Info: 5: + IC(0.456 ns) + CELL(0.590 ns) = 10.509 ns; Loc. = LC_X9_Y11_N7; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.046 ns" { lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.935 ns) 12.715 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N0 3 " "Info: 6: + IC(1.271 ns) + CELL(0.935 ns) = 12.715 ns; Loc. = LC_X8_Y12_N0; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "2.206 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.033 ns) + CELL(0.935 ns) 17.683 ns lcd:inst\|clk_int 7 REG LC_X9_Y10_N2 20 " "Info: 7: + IC(4.033 ns) + CELL(0.935 ns) = 17.683 ns; Loc. = LC_X9_Y10_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.968 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.889 ns) + CELL(0.711 ns) 22.283 ns lcd:inst\|counter\[5\] 8 REG LC_X4_Y15_N6 13 " "Info: 8: + IC(3.889 ns) + CELL(0.711 ns) = 22.283 ns; Loc. = LC_X4_Y15_N6; Fanout = 13; REG Node = 'lcd:inst\|counter\[5\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.600 ns" { lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 31.86 % " "Info: Total cell delay = 7.100 ns ( 31.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.183 ns 68.14 % " "Info: Total interconnect delay = 15.183 ns ( 68.14 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "22.283 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.283 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } { 0.000ns 0.000ns 0.745ns 3.509ns 1.280ns 0.456ns 1.271ns 4.033ns 3.889ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.705 ns + Longest register pin " "Info: + Longest register to pin delay is 16.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[5\] 1 REG LC_X4_Y15_N6 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y15_N6; Fanout = 13; REG Node = 'lcd:inst\|counter\[5\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|counter[5] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.292 ns) 1.900 ns lcd:inst\|LessThan~389 2 COMB LC_X2_Y14_N7 2 " "Info: 2: + IC(1.608 ns) + CELL(0.292 ns) = 1.900 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; COMB Node = 'lcd:inst\|LessThan~389'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.900 ns" { lcd:inst|counter[5] lcd:inst|LessThan~389 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.528 ns) + CELL(0.114 ns) 3.542 ns lcd:inst\|LessThan~390 3 COMB LC_X4_Y15_N0 3 " "Info: 3: + IC(1.528 ns) + CELL(0.114 ns) = 3.542 ns; Loc. = LC_X4_Y15_N0; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~390'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.642 ns" { lcd:inst|LessThan~389 lcd:inst|LessThan~390 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.292 ns) 5.090 ns lcd:inst\|char_addr~1508 4 COMB LC_X3_Y16_N8 3 " "Info: 4: + IC(1.256 ns) + CELL(0.292 ns) = 5.090 ns; Loc. = LC_X3_Y16_N8; Fanout = 3; COMB Node = 'lcd:inst\|char_addr~1508'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.548 ns" { lcd:inst|LessThan~390 lcd:inst|char_addr~1508 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.442 ns) 5.954 ns lcd:inst\|char_addr\[5\]~1514 5 COMB LC_X3_Y16_N4 5 " "Info: 5: + IC(0.422 ns) + CELL(0.442 ns) = 5.954 ns; Loc. = LC_X3_Y16_N4; Fanout = 5; COMB Node = 'lcd:inst\|char_addr\[5\]~1514'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.864 ns" { lcd:inst|char_addr~1508 lcd:inst|char_addr[5]~1514 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.442 ns) 7.125 ns lcd:inst\|char_addr\[2\]~1524 6 COMB LC_X4_Y16_N9 1 " "Info: 6: + IC(0.729 ns) + CELL(0.442 ns) = 7.125 ns; Loc. = LC_X4_Y16_N9; Fanout = 1; COMB Node = 'lcd:inst\|char_addr\[2\]~1524'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.171 ns" { lcd:inst|char_addr[5]~1514 lcd:inst|char_addr[2]~1524 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.292 ns) 8.507 ns lcd:inst\|char_addr\[2\]~1525 7 COMB LC_X2_Y16_N9 12 " "Info: 7: + IC(1.090 ns) + CELL(0.292 ns) = 8.507 ns; Loc. = LC_X2_Y16_N9; Fanout = 12; COMB Node = 'lcd:inst\|char_addr\[2\]~1525'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.382 ns" { lcd:inst|char_addr[2]~1524 lcd:inst|char_addr[2]~1525 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.442 ns) 9.760 ns lcd:inst\|char_ram:aa\|data\[3\]~1057 8 COMB LC_X1_Y16_N4 1 " "Info: 8: + IC(0.811 ns) + CELL(0.442 ns) = 9.760 ns; Loc. = LC_X1_Y16_N4; Fanout = 1; COMB Node = 'lcd:inst\|char_ram:aa\|data\[3\]~1057'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.253 ns" { lcd:inst|char_addr[2]~1525 lcd:inst|char_ram:aa|data[3]~1057 } "NODE_NAME" } "" } } { "../src/char_ram.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/char_ram.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.590 ns) 11.907 ns lcd:inst\|data~1216 9 COMB LC_X2_Y14_N5 1 " "Info: 9: + IC(1.557 ns) + CELL(0.590 ns) = 11.907 ns; Loc. = LC_X2_Y14_N5; Fanout = 1; COMB Node = 'lcd:inst\|data~1216'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "2.147 ns" { lcd:inst|char_ram:aa|data[3]~1057 lcd:inst|data~1216 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.590 ns) 13.227 ns lcd:inst\|data~1224 10 COMB LC_X2_Y14_N3 1 " "Info: 10: + IC(0.730 ns) + CELL(0.590 ns) = 13.227 ns; Loc. = LC_X2_Y14_N3; Fanout = 1; COMB Node = 'lcd:inst\|data~1224'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.320 ns" { lcd:inst|data~1216 lcd:inst|data~1224 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.354 ns) + CELL(2.124 ns) 16.705 ns LCD_D\[3\] 11 PIN PIN_20 0 " "Info: 11: + IC(1.354 ns) + CELL(2.124 ns) = 16.705 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'LCD_D\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "3.478 ns" { lcd:inst|data~1224 LCD_D[3] } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 272 736 912 288 "L