proj.tan.qmsg

基于ep1c6的vhdl的lcd控制程序实例

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 47 " "Warning: Circuit may not operate. Detected 47 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst\|state\[0\] lcd:inst\|state\[0\] clk 1.42 ns " "Info: Found hold time violation between source  pin or register \"lcd:inst\|state\[0\]\" and destination pin or register \"lcd:inst\|state\[0\]\" for clock \"clk\" (Hold time is 1.42 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.242 ns + Largest " "Info: + Largest clock skew is 2.242 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 22.283 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 22.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns div16:inst2\|count\[3\] 2 REG LC_X8_Y10_N6 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 17; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.680 ns" { clk div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns lcd:inst\|clkcnt\[6\] 3 REG LC_X8_Y12_N1 4 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X8_Y12_N1; Fanout = 4; REG Node = 'lcd:inst\|clkcnt\[6\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.444 ns" { div16:inst2|count[3] lcd:inst|clkcnt[6] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(0.590 ns) 9.463 ns lcd:inst\|reduce_nor~378 4 COMB LC_X9_Y11_N2 1 " "Info: 4: + IC(1.280 ns) + CELL(0.590 ns) = 9.463 ns; Loc. = LC_X9_Y11_N2; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~378'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.870 ns" { lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.590 ns) 10.509 ns lcd:inst\|reduce_nor~380 5 COMB LC_X9_Y11_N7 7 " "Info: 5: + IC(0.456 ns) + CELL(0.590 ns) = 10.509 ns; Loc. = LC_X9_Y11_N7; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.046 ns" { lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.935 ns) 12.715 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N0 3 " "Info: 6: + IC(1.271 ns) + CELL(0.935 ns) = 12.715 ns; Loc. = LC_X8_Y12_N0; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "2.206 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.033 ns) + CELL(0.935 ns) 17.683 ns lcd:inst\|clk_int 7 REG LC_X9_Y10_N2 20 " "Info: 7: + IC(4.033 ns) + CELL(0.935 ns) = 17.683 ns; Loc. = LC_X9_Y10_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.968 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.889 ns) + CELL(0.711 ns) 22.283 ns lcd:inst\|state\[0\] 8 REG LC_X3_Y15_N0 12 " "Info: 8: + IC(3.889 ns) + CELL(0.711 ns) = 22.283 ns; Loc. = LC_X3_Y15_N0; Fanout = 12; REG Node = 'lcd:inst\|state\[0\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.600 ns" { lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 31.86 % " "Info: Total cell delay = 7.100 ns ( 31.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.183 ns 68.14 % " "Info: Total interconnect delay = 15.183 ns ( 68.14 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "22.283 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.283 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } { 0.0ns 0.0ns 0.745ns 3.509ns 1.28ns 0.456ns 1.271ns 4.033ns 3.889ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.59ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 20.041 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 20.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns div16:inst2\|count\[3\] 2 REG LC_X8_Y10_N6 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 17; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.680 ns" { clk div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns lcd:inst\|clkcnt\[2\] 3 REG LC_X9_Y11_N6 3 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X9_Y11_N6; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[2\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.444 ns" { div16:inst2|count[3] lcd:inst|clkcnt[2] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 7.971 ns lcd:inst\|reduce_nor~379 4 COMB LC_X9_Y11_N6 1 " "Info: 4: + IC(0.000 ns) + CELL(0.378 ns) = 7.971 ns; Loc. = LC_X9_Y11_N6; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~379'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.378 ns" { lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.267 ns lcd:inst\|reduce_nor~380 5 COMB LC_X9_Y11_N7 7 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 8.267 ns; Loc. = LC_X9_Y11_N7; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.296 ns" { lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.935 ns) 10.473 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N0 3 " "Info: 6: + IC(1.271 ns) + CELL(0.935 ns) = 10.473 ns; Loc. = LC_X8_Y12_N0; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "2.206 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.033 ns) + CELL(0.935 ns) 15.441 ns lcd:inst\|clk_int 7 REG LC_X9_Y10_N2 20 " "Info: 7: + IC(4.033 ns) + CELL(0.935 ns) = 15.441 ns; Loc. = LC_X9_Y10_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.968 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.889 ns) + CELL(0.711 ns) 20.041 ns lcd:inst\|state\[0\] 8 REG LC_X3_Y15_N0 12 " "Info: 8: + IC(3.889 ns) + CELL(0.711 ns) = 20.041 ns; Loc. = LC_X3_Y15_N0; Fanout = 12; REG Node = 'lcd:inst\|state\[0\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.600 ns" { lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.412 ns 31.99 % " "Info: Total cell delay = 6.412 ns ( 31.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.629 ns 68.01 % " "Info: Total interconnect delay = 13.629 ns ( 68.01 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "20.041 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.041 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } { 0.0ns 0.0ns 0.745ns 3.509ns 0.0ns 0.182ns 1.271ns 4.033ns 3.889ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "22.283 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.283 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } { 0.0ns 0.0ns 0.745ns 3.509ns 1.28ns 0.456ns 1.271ns 4.033ns 3.889ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.59ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "20.041 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.041 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } { 0.0ns 0.0ns 0.745ns 3.509ns 0.0ns 0.182ns 1.271ns 4.033ns 3.889ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.613 ns - Shortest register register " "Info: - Shortest register to register delay is 0.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|state\[0\] 1 REG LC_X3_Y15_N0 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y15_N0; Fanout = 12; REG Node = 'lcd:inst\|state\[0\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|state[0] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.613 ns) 0.613 ns lcd:inst\|state\[0\] 2 REG LC_X3_Y15_N0 12 " "Info: 2: + IC(0.000 ns) + CELL(0.613 ns) = 0.613 ns; Loc. = LC_X3_Y15_N0; Fanout = 12; REG Node = 'lcd:inst\|state\[0\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.613 ns" { lcd:inst|state[0] lcd:inst|state[0] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.613 ns 100.00 % " "Info: Total cell delay = 0.613 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.613 ns" { lcd:inst|state[0] lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.613 ns" { lcd:inst|state[0] lcd:inst|state[0] } { 0.0ns 0.0ns } { 0.0ns 0.613ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "22.283 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.283 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } { 0.0ns 0.0ns 0.745ns 3.509ns 1.28ns 0.456ns 1.271ns 4.033ns 3.889ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.59ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "20.041 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.041 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[0] } { 0.0ns 0.0ns 0.745ns 3.509ns 0.0ns 0.182ns 1.271ns 4.033ns 3.889ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.613 ns" { lcd:inst|state[0] lcd:inst|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.613 ns" { lcd:inst|state[0] lcd:inst|state[0] } { 0.0ns 0.0ns } { 0.0ns 0.613ns } } }  } 0}