proj.tan.qmsg

基于ep1c6的vhdl的lcd控制程序实例

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[2\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[15\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[0\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[1\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[5\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[6\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[6\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[3\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[4\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[9\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[9\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[10\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[10\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[7\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[7\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[8\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[8\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[14\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[14\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[11\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[11\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~379 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~379\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~379" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~376 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~376\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~376" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~377 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~377\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~377" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst\|reduce_nor~378 " "Info: Detected gated clock \"lcd:inst\|reduce_nor~378\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|reduce_nor~378" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[12\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[12\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div16:inst2\|count\[3\] " "Info: Detected ripple clock \"div16:inst2\|count\[3\]\" as buffer" {  } { { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div16:inst2\|count\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst\|clkcnt\[13\]\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkcnt\[13\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clkdiv " "Info: Detected ripple clock \"lcd:inst\|clkdiv\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clkdiv" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst\|clk_int " "Info: Detected ripple clock \"lcd:inst\|clk_int\" as buffer" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst\|clk_int" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lcd:inst\|counter\[5\] register lcd:inst\|state\[9\] 104.88 MHz 9.535 ns Internal " "Info: Clock \"clk\" has Internal fmax of 104.88 MHz between source register \"lcd:inst\|counter\[5\]\" and destination register \"lcd:inst\|state\[9\]\" (period= 9.535 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.032 ns + Longest register register " "Info: + Longest register to register delay is 7.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[5\] 1 REG LC_X4_Y15_N6 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y15_N6; Fanout = 13; REG Node = 'lcd:inst\|counter\[5\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|counter[5] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.292 ns) 1.900 ns lcd:inst\|LessThan~389 2 COMB LC_X2_Y14_N7 2 " "Info: 2: + IC(1.608 ns) + CELL(0.292 ns) = 1.900 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; COMB Node = 'lcd:inst\|LessThan~389'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.900 ns" { lcd:inst|counter[5] lcd:inst|LessThan~389 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.528 ns) + CELL(0.114 ns) 3.542 ns lcd:inst\|LessThan~390 3 COMB LC_X4_Y15_N0 3 " "Info: 3: + IC(1.528 ns) + CELL(0.114 ns) = 3.542 ns; Loc. = LC_X4_Y15_N0; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~390'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.642 ns" { lcd:inst|LessThan~389 lcd:inst|LessThan~390 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.292 ns) 5.090 ns lcd:inst\|char_addr~1508 4 COMB LC_X3_Y16_N8 3 " "Info: 4: + IC(1.256 ns) + CELL(0.292 ns) = 5.090 ns; Loc. = LC_X3_Y16_N8; Fanout = 3; COMB Node = 'lcd:inst\|char_addr~1508'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.548 ns" { lcd:inst|LessThan~390 lcd:inst|char_addr~1508 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.738 ns) 7.032 ns lcd:inst\|state\[9\] 5 REG LC_X3_Y15_N9 7 " "Info: 5: + IC(1.204 ns) + CELL(0.738 ns) = 7.032 ns; Loc. = LC_X3_Y15_N9; Fanout = 7; REG Node = 'lcd:inst\|state\[9\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.942 ns" { lcd:inst|char_addr~1508 lcd:inst|state[9] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.436 ns 20.42 % " "Info: Total cell delay = 1.436 ns ( 20.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.596 ns 79.58 % " "Info: Total interconnect delay = 5.596 ns ( 79.58 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "7.032 ns" { lcd:inst|counter[5] lcd:inst|LessThan~389 lcd:inst|LessThan~390 lcd:inst|char_addr~1508 lcd:inst|state[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.032 ns" { lcd:inst|counter[5] lcd:inst|LessThan~389 lcd:inst|LessThan~390 lcd:inst|char_addr~1508 lcd:inst|state[9] } { 0.000ns 1.608ns 1.528ns 1.256ns 1.204ns } { 0.000ns 0.292ns 0.114ns 0.292ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.242 ns - Smallest " "Info: - Smallest clock skew is -2.242 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 20.041 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 20.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns div16:inst2\|count\[3\] 2 REG LC_X8_Y10_N6 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 17; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.680 ns" { clk div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns lcd:inst\|clkcnt\[2\] 3 REG LC_X9_Y11_N6 3 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X9_Y11_N6; Fanout = 3; REG Node = 'lcd:inst\|clkcnt\[2\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.444 ns" { div16:inst2|count[3] lcd:inst|clkcnt[2] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 7.971 ns lcd:inst\|reduce_nor~379 4 COMB LC_X9_Y11_N6 1 " "Info: 4: + IC(0.000 ns) + CELL(0.378 ns) = 7.971 ns; Loc. = LC_X9_Y11_N6; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~379'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.378 ns" { lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.267 ns lcd:inst\|reduce_nor~380 5 COMB LC_X9_Y11_N7 7 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 8.267 ns; Loc. = LC_X9_Y11_N7; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "0.296 ns" { lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.935 ns) 10.473 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N0 3 " "Info: 6: + IC(1.271 ns) + CELL(0.935 ns) = 10.473 ns; Loc. = LC_X8_Y12_N0; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "2.206 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.033 ns) + CELL(0.935 ns) 15.441 ns lcd:inst\|clk_int 7 REG LC_X9_Y10_N2 20 " "Info: 7: + IC(4.033 ns) + CELL(0.935 ns) = 15.441 ns; Loc. = LC_X9_Y10_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.968 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.889 ns) + CELL(0.711 ns) 20.041 ns lcd:inst\|state\[9\] 8 REG LC_X3_Y15_N9 7 " "Info: 8: + IC(3.889 ns) + CELL(0.711 ns) = 20.041 ns; Loc. = LC_X3_Y15_N9; Fanout = 7; REG Node = 'lcd:inst\|state\[9\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.600 ns" { lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.412 ns 31.99 % " "Info: Total cell delay = 6.412 ns ( 31.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.629 ns 68.01 % " "Info: Total interconnect delay = 13.629 ns ( 68.01 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "20.041 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.041 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } { 0.000ns 0.000ns 0.745ns 3.509ns 0.000ns 0.182ns 1.271ns 4.033ns 3.889ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 22.283 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 22.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 88 232 400 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns div16:inst2\|count\[3\] 2 REG LC_X8_Y10_N6 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 17; REG Node = 'div16:inst2\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.680 ns" { clk div16:inst2|count[3] } "NODE_NAME" } "" } } { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns lcd:inst\|clkcnt\[6\] 3 REG LC_X8_Y12_N1 4 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X8_Y12_N1; Fanout = 4; REG Node = 'lcd:inst\|clkcnt\[6\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.444 ns" { div16:inst2|count[3] lcd:inst|clkcnt[6] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(0.590 ns) 9.463 ns lcd:inst\|reduce_nor~378 4 COMB LC_X9_Y11_N2 1 " "Info: 4: + IC(1.280 ns) + CELL(0.590 ns) = 9.463 ns; Loc. = LC_X9_Y11_N2; Fanout = 1; COMB Node = 'lcd:inst\|reduce_nor~378'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.870 ns" { lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.590 ns) 10.509 ns lcd:inst\|reduce_nor~380 5 COMB LC_X9_Y11_N7 7 " "Info: 5: + IC(0.456 ns) + CELL(0.590 ns) = 10.509 ns; Loc. = LC_X9_Y11_N7; Fanout = 7; COMB Node = 'lcd:inst\|reduce_nor~380'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.046 ns" { lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.935 ns) 12.715 ns lcd:inst\|clkdiv 6 REG LC_X8_Y12_N0 3 " "Info: 6: + IC(1.271 ns) + CELL(0.935 ns) = 12.715 ns; Loc. = LC_X8_Y12_N0; Fanout = 3; REG Node = 'lcd:inst\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "2.206 ns" { lcd:inst|reduce_nor~380 lcd:inst|clkdiv } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 75 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.033 ns) + CELL(0.935 ns) 17.683 ns lcd:inst\|clk_int 7 REG LC_X9_Y10_N2 20 " "Info: 7: + IC(4.033 ns) + CELL(0.935 ns) = 17.683 ns; Loc. = LC_X9_Y10_N2; Fanout = 20; REG Node = 'lcd:inst\|clk_int'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.968 ns" { lcd:inst|clkdiv lcd:inst|clk_int } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 71 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.889 ns) + CELL(0.711 ns) 22.283 ns lcd:inst\|counter\[5\] 8 REG LC_X4_Y15_N6 13 " "Info: 8: + IC(3.889 ns) + CELL(0.711 ns) = 22.283 ns; Loc. = LC_X4_Y15_N6; Fanout = 13; REG Node = 'lcd:inst\|counter\[5\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "4.600 ns" { lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 31.86 % " "Info: Total cell delay = 7.100 ns ( 31.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.183 ns 68.14 % " "Info: Total interconnect delay = 15.183 ns ( 68.14 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "22.283 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.283 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } { 0.000ns 0.000ns 0.745ns 3.509ns 1.280ns 0.456ns 1.271ns 4.033ns 3.889ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "20.041 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.041 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } { 0.000ns 0.000ns 0.745ns 3.509ns 0.000ns 0.182ns 1.271ns 4.033ns 3.889ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "22.283 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.283 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } { 0.000ns 0.000ns 0.745ns 3.509ns 1.280ns 0.456ns 1.271ns 4.033ns 3.889ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "7.032 ns" { lcd:inst|counter[5] lcd:inst|LessThan~389 lcd:inst|LessThan~390 lcd:inst|char_addr~1508 lcd:inst|state[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.032 ns" { lcd:inst|counter[5] lcd:inst|LessThan~389 lcd:inst|LessThan~390 lcd:inst|char_addr~1508 lcd:inst|state[9] } { 0.000ns 1.608ns 1.528ns 1.256ns 1.204ns } { 0.000ns 0.292ns 0.114ns 0.292ns 0.738ns } } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "20.041 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "20.041 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[2] lcd:inst|reduce_nor~379 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|state[9] } { 0.000ns 0.000ns 0.745ns 3.509ns 0.000ns 0.182ns 1.271ns 4.033ns 3.889ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.378ns 0.114ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "22.283 ns" { clk div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "22.283 ns" { clk clk~out0 div16:inst2|count[3] lcd:inst|clkcnt[6] lcd:inst|reduce_nor~378 lcd:inst|reduce_nor~380 lcd:inst|clkdiv lcd:inst|clk_int lcd:inst|counter[5] } { 0.000ns 0.000ns 0.745ns 3.509ns 1.280ns 0.456ns 1.271ns 4.033ns 3.889ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.935ns 0.935ns 0.711ns } } }  } 0}