proj.fit.qmsg

基于ep1c6的vhdl的lcd控制程序实例

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 13 31 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 13 total pin(s) used --  31 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 2 43 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  43 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.400 ns register register " "Info: Estimated most critical path is register to register delay of 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|counter\[3\] 1 REG LAB_X4_Y15 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y15; Fanout = 15; REG Node = 'lcd:inst\|counter\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { lcd:inst|counter[3] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.482 ns) + CELL(0.292 ns) 1.774 ns lcd:inst\|LessThan~389 2 COMB LAB_X2_Y14 2 " "Info: 2: + IC(1.482 ns) + CELL(0.292 ns) = 1.774 ns; Loc. = LAB_X2_Y14; Fanout = 2; COMB Node = 'lcd:inst\|LessThan~389'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.774 ns" { lcd:inst|counter[3] lcd:inst|LessThan~389 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.292 ns) 3.472 ns lcd:inst\|LessThan~390 3 COMB LAB_X4_Y15 3 " "Info: 3: + IC(1.406 ns) + CELL(0.292 ns) = 3.472 ns; Loc. = LAB_X4_Y15; Fanout = 3; COMB Node = 'lcd:inst\|LessThan~390'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.698 ns" { lcd:inst|LessThan~389 lcd:inst|LessThan~390 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.442 ns) 4.843 ns lcd:inst\|char_addr~1508 4 COMB LAB_X3_Y16 3 " "Info: 4: + IC(0.929 ns) + CELL(0.442 ns) = 4.843 ns; Loc. = LAB_X3_Y16; Fanout = 3; COMB Node = 'lcd:inst\|char_addr~1508'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.371 ns" { lcd:inst|LessThan~390 lcd:inst|char_addr~1508 } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.478 ns) 6.400 ns lcd:inst\|state\[9\] 5 REG LAB_X3_Y15 7 " "Info: 5: + IC(1.079 ns) + CELL(0.478 ns) = 6.400 ns; Loc. = LAB_X3_Y15; Fanout = 7; REG Node = 'lcd:inst\|state\[9\]'" {  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "1.557 ns" { lcd:inst|char_addr~1508 lcd:inst|state[9] } "NODE_NAME" } "" } } { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.504 ns 23.50 % " "Info: Total cell delay = 1.504 ns ( 23.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.896 ns 76.50 % " "Info: Total interconnect delay = 4.896 ns ( 76.50 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "6.400 ns" { lcd:inst|counter[3] lcd:inst|LessThan~389 lcd:inst|LessThan~390 lcd:inst|char_addr~1508 lcd:inst|state[9] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DIR VCC " "Info: Pin LCD_DIR has VCC driving its datain port" {  } { { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 352 784 960 368 "LCD_DIR" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "LCD_DIR" } } } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/Proj_cmp.qrpt" Compiler "Proj" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_VHDL/Proj/db/LCD_Test.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/" "" "" { LCD_DIR } "NODE_NAME" } "" } } { "E:/code/EP1C6/S4_LCD_VHDL/Proj/Proj.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_VHDL/Proj/Proj.fld" "" "" { LCD_DIR } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 10:06:47 2006 " "Info: Processing ended: Thu Feb 23 10:06:47 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}