proj.map.qmsg

基于ep1c6的vhdl的lcd控制程序实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 23 10:06:37 2006 " "Info: Processing started: Thu Feb 23 10:06:37 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LCD_Test -c Proj " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD_Test -c Proj" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/char_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../src/char_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 char_ram-fun " "Info: Found design unit 1: char_ram-fun" {  } { { "../src/char_ram.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/char_ram.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 char_ram " "Info: Found entity 1: char_ram" {  } { { "../src/char_ram.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/char_ram.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/div16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../src/div16.v" { { "Info" "ISGN_ENTITY_NAME" "1 div16 " "Info: Found entity 1: div16" {  } { { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/lcd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../src/lcd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd-Behavioral " "Info: Found design unit 1: lcd-Behavioral" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_test " "Info: Found entity 1: lcd_test" {  } { { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_test " "Info: Elaborating entity \"lcd_test\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "lcd_e lcd inst " "Warning: Port \"lcd_e\" of type lcd and instance \"inst\" is missing source signal" {  } { { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 200 528 680 328 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst\"" {  } { { "lcd_test.bdf" "inst" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 200 528 680 328 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "char_ram lcd:inst\|char_ram:aa " "Info: Elaborating entity \"char_ram\" for hierarchy \"lcd:inst\|char_ram:aa\"" {  } { { "../src/lcd.vhd" "aa" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 126 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div16 div16:inst2 " "Info: Elaborating entity \"div16\" for hierarchy \"div16:inst2\"" {  } { { "lcd_test.bdf" "inst2" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 64 488 584 160 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 div16.v(10) " "Warning: Verilog HDL assignment warning at div16.v(10): truncated value with size 32 to match size of target (4)" {  } { { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 10 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 div16.v(12) " "Warning: Verilog HDL assignment warning at div16.v(12): truncated value with size 32 to match size of target (4)" {  } { { "../src/div16.v" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/div16.v" 12 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[10\] data_in GND " "Warning: Reduced register \"lcd:inst\|state\[10\]\" with stuck data_in port to stuck value GND" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[8\] data_in GND " "Warning: Reduced register \"lcd:inst\|state\[8\]\" with stuck data_in port to stuck value GND" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[6\] data_in GND " "Warning: Reduced register \"lcd:inst\|state\[6\]\" with stuck data_in port to stuck value GND" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lcd:inst\|state\[1\] data_in GND " "Warning: Reduced register \"lcd:inst\|state\[1\]\" with stuck data_in port to stuck value GND" {  } { { "../src/lcd.vhd" "" { Text "E:/code/EP1C6/S4_LCD_VHDL/src/lcd.vhd" 56 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_DIR VCC " "Warning: Pin \"LCD_DIR\" stuck at VCC" {  } { { "lcd_test.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_VHDL/Proj/lcd_test.bdf" { { 352 784 960 368 "LCD_DIR" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "181 " "Info: Implemented 181 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "167 " "Info: Implemented 167 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 10:06:41 2006 " "Info: Processing ended: Thu Feb 23 10:06:41 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}