pc2fpga.tan.qmsg

cy7c68013向外部发送一个数据

{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_149 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[13\] rst clk 6.277 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[13\]\" (data pin = \"rst\", clock pin = \"clk\") is 6.277 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.890 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.890 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.284 ns) + CELL(0.935 ns) 4.688 ns clkin 2 REG LC_X8_Y10_N2 176 " "Info: 2: + IC(2.284 ns) + CELL(0.935 ns) = 4.688 ns; Loc. = LC_X8_Y10_N2; Fanout = 176; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "3.219 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.491 ns) + CELL(0.711 ns) 8.890 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[13\] 3 REG LC_X13_Y6_N3 3 " "Info: 3: + IC(3.491 ns) + CELL(0.711 ns) = 8.890 ns; Loc. = LC_X13_Y6_N3; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[13\]'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.202 ns" { clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 35.04 % " "Info: Total cell delay = 3.115 ns ( 35.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.775 ns 64.96 % " "Info: Total interconnect delay = 5.775 ns ( 64.96 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.890 ns" { clk clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.890 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } { 0.000ns 0.000ns 2.284ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.628 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_131 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 5; PIN Node = 'rst'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { rst } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.115 ns) 2.628 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[13\] 2 REG LC_X13_Y6_N3 3 " "Info: 2: + IC(1.044 ns) + CELL(0.115 ns) = 2.628 ns; Loc. = LC_X13_Y6_N3; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[13\]'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.159 ns" { rst sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns 60.27 % " "Info: Total cell delay = 1.584 ns ( 60.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.044 ns 39.73 % " "Info: Total interconnect delay = 1.044 ns ( 39.73 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "2.628 ns" { rst sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.628 ns" { rst rst~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } { 0.000ns 0.000ns 1.044ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.890 ns" { clk clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.890 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } { 0.000ns 0.000ns 2.284ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "2.628 ns" { rst sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.628 ns" { rst rst~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13] } { 0.000ns 0.000ns 1.044ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 10:23:35 2006 " "Info: Processing ended: Thu Feb 23 10:23:35 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}