pc2fpga.tan.qmsg

cy7c68013向外部发送一个数据

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|hub_tdo 109.12 MHz 9.164 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 109.12 MHz between source register \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 9.164 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.305 ns + Longest register register " "Info: + Longest register to register delay is 4.305 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LC_X12_Y10_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.284 ns) + CELL(0.442 ns) 1.726 ns sld_hub:sld_hub_inst\|hub_tdo~277 2 COMB LC_X11_Y8_N4 1 " "Info: 2: + IC(1.284 ns) + CELL(0.442 ns) = 1.726 ns; Loc. = LC_X11_Y8_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~277'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.726 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.292 ns) 3.297 ns sld_hub:sld_hub_inst\|hub_tdo~278 3 COMB LC_X12_Y9_N0 1 " "Info: 3: + IC(1.279 ns) + CELL(0.292 ns) = 3.297 ns; Loc. = LC_X12_Y9_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~278'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.571 ns" { sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.607 ns) 4.305 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X12_Y9_N5 0 " "Info: 4: + IC(0.401 ns) + CELL(0.607 ns) = 4.305 ns; Loc. = LC_X12_Y9_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.008 ns" { sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.341 ns 31.15 % " "Info: Total cell delay = 1.341 ns ( 31.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.964 ns 68.85 % " "Info: Total interconnect delay = 2.964 ns ( 68.85 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.305 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.305 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.284ns 1.279ns 0.401ns } { 0.000ns 0.442ns 0.292ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.016 ns - Smallest " "Info: - Smallest clock skew is -0.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.276 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.276 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.565 ns) + CELL(0.711 ns) 5.276 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X12_Y9_N5 0 " "Info: 2: + IC(4.565 ns) + CELL(0.711 ns) = 5.276 ns; Loc. = LC_X12_Y9_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.276 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.48 % " "Info: Total cell delay = 0.711 ns ( 13.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.565 ns 86.52 % " "Info: Total interconnect delay = 4.565 ns ( 86.52 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.276 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.276 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.565ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.292 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 230 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 230; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 2 REG LC_X12_Y10_N8 1 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X12_Y10_N8; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 % " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.276 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.276 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.565ns } { 0.000ns 0.711ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.305 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.305 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.284ns 1.279ns 0.401ns } { 0.000ns 0.442ns 0.292ns 0.607ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.276 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.276 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.565ns } { 0.000ns 0.711ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "STATE.READ_1 fifo_empty clk 0.195 ns register " "Info: tsu for register \"STATE.READ_1\" (data pin = \"fifo_empty\", clock pin = \"clk\") is 0.195 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.046 ns + Longest pin register " "Info: + Longest pin to register delay is 9.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fifo_empty 1 PIN PIN_53 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_53; Fanout = 3; PIN Node = 'fifo_empty'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { fifo_empty } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.839 ns) + CELL(0.738 ns) 9.046 ns STATE.READ_1 2 REG LC_X13_Y5_N2 3 " "Info: 2: + IC(6.839 ns) + CELL(0.738 ns) = 9.046 ns; Loc. = LC_X13_Y5_N2; Fanout = 3; REG Node = 'STATE.READ_1'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "7.577 ns" { fifo_empty STATE.READ_1 } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns 24.40 % " "Info: Total cell delay = 2.207 ns ( 24.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.839 ns 75.60 % " "Info: Total interconnect delay = 6.839 ns ( 75.60 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "9.046 ns" { fifo_empty STATE.READ_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.046 ns" { fifo_empty fifo_empty~out0 STATE.READ_1 } { 0.000ns 0.000ns 6.839ns } { 0.000ns 1.469ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.888 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.284 ns) + CELL(0.935 ns) 4.688 ns clkin 2 REG LC_X8_Y10_N2 176 " "Info: 2: + IC(2.284 ns) + CELL(0.935 ns) = 4.688 ns; Loc. = LC_X8_Y10_N2; Fanout = 176; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "3.219 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.489 ns) + CELL(0.711 ns) 8.888 ns STATE.READ_1 3 REG LC_X13_Y5_N2 3 " "Info: 3: + IC(3.489 ns) + CELL(0.711 ns) = 8.888 ns; Loc. = LC_X13_Y5_N2; Fanout = 3; REG Node = 'STATE.READ_1'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.200 ns" { clkin STATE.READ_1 } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 35.05 % " "Info: Total cell delay = 3.115 ns ( 35.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.773 ns 64.95 % " "Info: Total interconnect delay = 5.773 ns ( 64.95 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.888 ns" { clk clkin STATE.READ_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.888 ns" { clk clk~out0 clkin STATE.READ_1 } { 0.000ns 0.000ns 2.284ns 3.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "9.046 ns" { fifo_empty STATE.READ_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.046 ns" { fifo_empty fifo_empty~out0 STATE.READ_1 } { 0.000ns 0.000ns 6.839ns } { 0.000ns 1.469ns 0.738ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.888 ns" { clk clkin STATE.READ_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.888 ns" { clk clk~out0 clkin STATE.READ_1 } { 0.000ns 0.000ns 2.284ns 3.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fifo_rd fifo_rd~reg0 13.800 ns register " "Info: tco from clock \"clk\" to destination pin \"fifo_rd\" through register \"fifo_rd~reg0\" is 13.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.888 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.284 ns) + CELL(0.935 ns) 4.688 ns clkin 2 REG LC_X8_Y10_N2 176 " "Info: 2: + IC(2.284 ns) + CELL(0.935 ns) = 4.688 ns; Loc. = LC_X8_Y10_N2; Fanout = 176; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "3.219 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.489 ns) + CELL(0.711 ns) 8.888 ns fifo_rd~reg0 3 REG LC_X13_Y5_N9 4 " "Info: 3: + IC(3.489 ns) + CELL(0.711 ns) = 8.888 ns; Loc. = LC_X13_Y5_N9; Fanout = 4; REG Node = 'fifo_rd~reg0'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.200 ns" { clkin fifo_rd~reg0 } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 35.05 % " "Info: Total cell delay = 3.115 ns ( 35.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.773 ns 64.95 % " "Info: Total interconnect delay = 5.773 ns ( 64.95 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.888 ns" { clk clkin fifo_rd~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.888 ns" { clk clk~out0 clkin fifo_rd~reg0 } { 0.000ns 0.000ns 2.284ns 3.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.688 ns + Longest register pin " "Info: + Longest register to pin delay is 4.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_rd~reg0 1 REG LC_X13_Y5_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y5_N9; Fanout = 4; REG Node = 'fifo_rd~reg0'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { fifo_rd~reg0 } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.564 ns) + CELL(2.124 ns) 4.688 ns fifo_rd 2 PIN PIN_57 0 " "Info: 2: + IC(2.564 ns) + CELL(2.124 ns) = 4.688 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'fifo_rd'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.688 ns" { fifo_rd~reg0 fifo_rd } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 45.31 % " "Info: Total cell delay = 2.124 ns ( 45.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.564 ns 54.69 % " "Info: Total interconnect delay = 2.564 ns ( 54.69 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.688 ns" { fifo_rd~reg0 fifo_rd } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.688 ns" { fifo_rd~reg0 fifo_rd } { 0.000ns 2.564ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.888 ns" { clk clkin fifo_rd~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.888 ns" { clk clk~out0 clkin fifo_rd~reg0 } { 0.000ns 0.000ns 2.284ns 3.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.688 ns" { fifo_rd~reg0 fifo_rd } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.688 ns" { fifo_rd~reg0 fifo_rd } { 0.000ns 2.564ns } { 0.000ns 2.124ns } } }  } 0}