pc2fpga.tan.rpt

cy7c68013向外部发送一个数据

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                                                                    ; To                                                                                                                                                   ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 0.195 ns                         ; fifo_empty                                                                                                                                                                                                              ; STATE.READ_1                                                                                                                                         ;                              ; clk                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 13.800 ns                        ; fifo_rd~reg0                                                                                                                                                                                                            ; fifo_rd                                                                                                                                              ; clk                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                ; altera_reserved_tdo                                                                                                                                  ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 6.277 ns                         ; rst                                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13]                                                                                                ;                              ; clk                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 109.12 MHz ( period = 9.164 ns ) ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                                                                 ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                         ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 127.23 MHz ( period = 7.860 ns ) ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; clk                          ; clk                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                                                                         ;                                                                                                                                                      ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;