fpga2pc.qsf

usb芯片cy7c68013从fpga中读入数据的演示程序

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		fpga2pc_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.2 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:01:10  MAY 07, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VERILOG_FILE ../Src/fpga2pc.v
set_global_assignment -name SIGNALTAP_FILE fpga2pc.stp
set_global_assignment -name SIGNALTAP_FILE "D:\\RedLogic\\RCII_samples\\USB_IN\\Proj\\fpga2pc.stp"

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_153 -to clk
set_location_assignment PIN_58 -to fifo_data[0]
set_location_assignment PIN_59 -to fifo_data[1]
set_location_assignment PIN_60 -to fifo_data[2]
set_location_assignment PIN_61 -to fifo_data[3]
set_location_assignment PIN_62 -to fifo_data[4]
set_location_assignment PIN_63 -to fifo_data[5]
set_location_assignment PIN_64 -to fifo_data[6]
set_location_assignment PIN_65 -to fifo_data[7]
set_location_assignment PIN_53 -to fifo_empty
set_location_assignment PIN_54 -to fifo_full
set_location_assignment PIN_55 -to fifo_pf
set_location_assignment PIN_57 -to fifo_rd
set_location_assignment PIN_56 -to fifo_wr
set_location_assignment PIN_131 -to rst

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY fpga2pc
set_global_assignment -name USER_LIBRARIES "f:\\i2c_altera/"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP On
set_global_assignment -name USE_SIGNALTAP_FILE "D:\\RedLogic\\RCII_samples\\USB_IN\\Proj\\fpga2pc.stp"