fpga2pc.tan.rpt

usb芯片cy7c68013从fpga中读入数据的演示程序

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.IDLE        ; STATE.IDLE        ; clk        ; clk      ; None                        ; None                      ; 1.014 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkin             ; clkin             ; clk        ; clk      ; None                        ; None                      ; 1.014 ns                ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------+
; tsu                                                                          ;
+-------+--------------+------------+-----------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From      ; To                ; To Clock ;
+-------+--------------+------------+-----------+-------------------+----------+
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[0]~reg0 ; clk      ;
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[1]~reg0 ; clk      ;
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[2]~reg0 ; clk      ;
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[3]~reg0 ; clk      ;
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[4]~reg0 ; clk      ;
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[5]~reg0 ; clk      ;
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[6]~reg0 ; clk      ;
; N/A   ; None         ; 0.028 ns   ; fifo_full ; fifo_data[7]~reg0 ; clk      ;
; N/A   ; None         ; -1.158 ns  ; fifo_full ; STATE.WRITE_2     ; clk      ;
; N/A   ; None         ; -1.160 ns  ; fifo_full ; STATE.WRITE_1     ; clk      ;
+-------+--------------+------------+-----------+-------------------+----------+


+-----------------------------------------------------------------------------------+
; tco                                                                               ;
+-------+--------------+------------+-------------------+--------------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To           ; From Clock ;
+-------+--------------+------------+-------------------+--------------+------------+
; N/A   ; None         ; 14.078 ns  ; fifo_data[7]~reg0 ; fifo_data[7] ; clk        ;
; N/A   ; None         ; 13.914 ns  ; fifo_data[1]~reg0 ; fifo_data[1] ; clk        ;
; N/A   ; None         ; 13.850 ns  ; fifo_data[2]~reg0 ; fifo_data[2] ; clk        ;
; N/A   ; None         ; 13.821 ns  ; fifo_data[0]~reg0 ; fifo_data[0] ; clk        ;
; N/A   ; None         ; 13.748 ns  ; fifo_data[4]~reg0 ; fifo_data[4] ; clk        ;
; N/A   ; None         ; 13.724 ns  ; fifo_data[6]~reg0 ; fifo_data[6] ; clk        ;
; N/A   ; None         ; 13.684 ns  ; fifo_data[5]~reg0 ; fifo_data[5] ; clk        ;
; N/A   ; None         ; 13.674 ns  ; fifo_data[3]~reg0 ; fifo_data[3] ; clk        ;
; N/A   ; None         ; 13.572 ns  ; fifo_wr~reg0      ; fifo_wr      ; clk        ;
+-------+--------------+------------+-------------------+--------------+------------+


+------------------------------------------------------------------------------------+
; th                                                                                 ;
+---------------+-------------+-----------+-----------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                ; To Clock ;
+---------------+-------------+-----------+-----------+-------------------+----------+
; N/A           ; None        ; 1.212 ns  ; fifo_full ; STATE.WRITE_1     ; clk      ;
; N/A           ; None        ; 1.210 ns  ; fifo_full ; STATE.WRITE_2     ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[0]~reg0 ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[1]~reg0 ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[2]~reg0 ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[3]~reg0 ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[4]~reg0 ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[5]~reg0 ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[6]~reg0 ; clk      ;
; N/A           ; None        ; 0.024 ns  ; fifo_full ; fifo_data[7]~reg0 ; clk      ;
+---------------+-------------+-----------+-----------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Thu Feb 23 15:01:25 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off USB_IN -c fpga2pc --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clkin" as buffer
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "fifo_data[1]~reg0" and destination register "fifo_data[7]~reg0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.266 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y9_N1; Fanout = 4; REG Node = 'fifo_data[1]~reg0'
            Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X2_Y9_N1; Fanout = 2; COMB Node = 'fifo_data[1]~97'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; COMB Node = 'fifo_data[2]~101'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X2_Y9_N3; Fanout = 2; COMB Node = 'fifo_data[3]~105'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X2_Y9_N4; Fanout = 3; COMB Node = 'fifo_data[4]~109'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data[7]~reg0'
            Info: Total cell delay = 1.737 ns ( 76.65 % )
            Info: Total interconnect delay = 0.529 ns ( 23.35 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 9.191 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'
                Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data[7]~reg0'
                Info: Total cell delay = 3.115 ns ( 33.89 % )
                Info: Total interconnect delay = 6.076 ns ( 66.11 % )
            Info: - Longest clock path from clock "clk" to source register is 9.191 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'
                Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N1; Fanout = 4; REG Node = 'fifo_data[1]~reg0'
                Info: Total cell delay = 3.115 ns ( 33.89 % )
                Info: Total interconnect delay = 6.076 ns ( 66.11 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "fifo_data[0]~reg0" (data pin = "fifo_full", clock pin = "clk") is 0.028 ns
    Info: + Longest pin to register delay is 9.182 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_54; Fanout = 3; PIN Node = 'fifo_full'
        Info: 2: + IC(5.789 ns) + CELL(0.590 ns) = 7.848 ns; Loc. = LC_X2_Y9_N9; Fanout = 8; COMB Node = 'fifo_data[7]~8'
        Info: 3: + IC(0.467 ns) + CELL(0.867 ns) = 9.182 ns; Loc. = LC_X2_Y9_N0; Fanout = 4; REG Node = 'fifo_data[0]~reg0'
        Info: Total cell delay = 2.926 ns ( 31.87 % )
        Info: Total interconnect delay = 6.256 ns ( 68.13 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 9.191 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'
        Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N0; Fanout = 4; REG Node = 'fifo_data[0]~reg0'
        Info: Total cell delay = 3.115 ns ( 33.89 % )
        Info: Total interconnect delay = 6.076 ns ( 66.11 % )
Info: tco from clock "clk" to destination pin "fifo_data[7]" through register "fifo_data[7]~reg0" is 14.078 ns
    Info: + Longest clock path from clock "clk" to source register is 9.191 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'
        Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data[7]~reg0'
        Info: Total cell delay = 3.115 ns ( 33.89 % )
        Info: Total interconnect delay = 6.076 ns ( 66.11 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y9_N7; Fanout = 2; REG Node = 'fifo_data[7]~reg0'
        Info: 2: + IC(2.555 ns) + CELL(2.108 ns) = 4.663 ns; Loc. = PIN_65; Fanout = 0; PIN Node = 'fifo_data[7]'
        Info: Total cell delay = 2.108 ns ( 45.21 % )
        Info: Total interconnect delay = 2.555 ns ( 54.79 % )
Info: th for register "STATE.WRITE_1" (data pin = "fifo_full", clock pin = "clk") is 1.212 ns
    Info: + Longest clock path from clock "clk" to destination register is 9.191 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'
        Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N8; Fanout = 5; REG Node = 'STATE.WRITE_1'
        Info: Total cell delay = 3.115 ns ( 33.89 % )
        Info: Total interconnect delay = 6.076 ns ( 66.11 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.994 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_54; Fanout = 3; PIN Node = 'fifo_full'
        Info: 2: + IC(5.787 ns) + CELL(0.738 ns) = 7.994 ns; Loc. = LC_X2_Y9_N8; Fanout = 5; REG Node = 'STATE.WRITE_1'
        Info: Total cell delay = 2.207 ns ( 27.61 % )
        Info: Total interconnect delay = 5.787 ns ( 72.39 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Feb 23 15:01:25 2006
    Info: Elapsed time: 00:00:02