📄 fpga2pc.tan.rpt
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Timing Analyzer report for fpga2pc
Thu Feb 23 15:01:25 2006
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 0.028 ns ; fifo_full ; fifo_data[7]~reg0 ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 14.078 ns ; fifo_data[7]~reg0 ; fifo_data[7] ; clk ; ; 0 ;
; Worst-case th ; N/A ; None ; 1.212 ns ; fifo_full ; STATE.WRITE_1 ; ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[5]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 2.266 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 2.266 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[5]~reg0 ; clk ; clk ; None ; None ; 2.266 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[5]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 2.200 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[2]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 2.191 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[2]~reg0 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 2.191 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[2]~reg0 ; fifo_data[5]~reg0 ; clk ; clk ; None ; None ; 2.191 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[5]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[4]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[3]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[2]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[1]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_data[0]~reg0 ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 2.179 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 2.179 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[5]~reg0 ; clk ; clk ; None ; None ; 2.179 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[5]~reg0 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 2.120 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[4]~reg0 ; clk ; clk ; None ; None ; 2.051 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[2]~reg0 ; fifo_data[4]~reg0 ; clk ; clk ; None ; None ; 1.974 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[3]~reg0 ; clk ; clk ; None ; None ; 1.971 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[4]~reg0 ; clk ; clk ; None ; None ; 1.964 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[3]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[3]~reg0 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[3]~reg0 ; fifo_data[5]~reg0 ; clk ; clk ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[4]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 1.932 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[4]~reg0 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 1.932 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[4]~reg0 ; fifo_data[5]~reg0 ; clk ; clk ; None ; None ; 1.932 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[2]~reg0 ; fifo_data[3]~reg0 ; clk ; clk ; None ; None ; 1.894 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[6]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 1.891 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[2]~reg0 ; clk ; clk ; None ; None ; 1.891 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[3]~reg0 ; clk ; clk ; None ; None ; 1.884 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[2]~reg0 ; clk ; clk ; None ; None ; 1.804 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[3]~reg0 ; fifo_data[4]~reg0 ; clk ; clk ; None ; None ; 1.725 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[1]~reg0 ; clk ; clk ; None ; None ; 1.724 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; STATE.IDLE ; clk ; clk ; None ; None ; 1.508 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[5]~reg0 ; fifo_data[5]~reg0 ; clk ; clk ; None ; None ; 1.496 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_2 ; STATE.WRITE_1 ; clk ; clk ; None ; None ; 1.407 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.IDLE ; STATE.WRITE_1 ; clk ; clk ; None ; None ; 1.333 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[7]~reg0 ; fifo_data[7]~reg0 ; clk ; clk ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[2]~reg0 ; fifo_data[2]~reg0 ; clk ; clk ; None ; None ; 1.270 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[6]~reg0 ; fifo_data[6]~reg0 ; clk ; clk ; None ; None ; 1.267 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[1]~reg0 ; fifo_data[1]~reg0 ; clk ; clk ; None ; None ; 1.267 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[4]~reg0 ; fifo_data[4]~reg0 ; clk ; clk ; None ; None ; 1.117 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[3]~reg0 ; fifo_data[3]~reg0 ; clk ; clk ; None ; None ; 1.113 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fifo_data[0]~reg0 ; fifo_data[0]~reg0 ; clk ; clk ; None ; None ; 1.112 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; fifo_wr~reg0 ; clk ; clk ; None ; None ; 1.070 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_2 ; STATE.IDLE ; clk ; clk ; None ; None ; 1.056 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; STATE.WRITE_2 ; clk ; clk ; None ; None ; 1.036 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; STATE.WRITE_1 ; STATE.WRITE_1 ; clk ; clk ; None ; None ; 1.036 ns ;
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