fpga2pc.fit.eqn

usb芯片cy7c68013从fpga中读入数据的演示程序

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--A1L44Q is fifo_wr~reg0 at LC_X1_Y9_N4
--operation mode is normal

A1L44Q_lut_out = STATE.WRITE_1;
A1L44Q = DFFEAS(A1L44Q_lut_out, !GLOBAL(clkin), GLOBAL(rst), , , , , , );


--A1L01Q is fifo_data[0]~reg0 at LC_X2_Y9_N0
--operation mode is arithmetic

A1L01Q_lut_out = !A1L01Q;
A1L01Q = DFFEAS(A1L01Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );

--A1L8 is fifo_data[0]~93 at LC_X2_Y9_N0
--operation mode is arithmetic

A1L8_cout_0 = A1L01Q;
A1L8 = CARRY(A1L8_cout_0);

--A1L9 is fifo_data[0]~93COUT1_125 at LC_X2_Y9_N0
--operation mode is arithmetic

A1L9_cout_1 = A1L01Q;
A1L9 = CARRY(A1L9_cout_1);


--A1L41Q is fifo_data[1]~reg0 at LC_X2_Y9_N1
--operation mode is arithmetic

A1L41Q_lut_out = A1L41Q $ (A1L8);
A1L41Q = DFFEAS(A1L41Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );

--A1L21 is fifo_data[1]~97 at LC_X2_Y9_N1
--operation mode is arithmetic

A1L21_cout_0 = !A1L8 # !A1L41Q;
A1L21 = CARRY(A1L21_cout_0);

--A1L31 is fifo_data[1]~97COUT1_126 at LC_X2_Y9_N1
--operation mode is arithmetic

A1L31_cout_1 = !A1L9 # !A1L41Q;
A1L31 = CARRY(A1L31_cout_1);


--A1L81Q is fifo_data[2]~reg0 at LC_X2_Y9_N2
--operation mode is arithmetic

A1L81Q_lut_out = A1L81Q $ (!A1L21);
A1L81Q = DFFEAS(A1L81Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );

--A1L61 is fifo_data[2]~101 at LC_X2_Y9_N2
--operation mode is arithmetic

A1L61_cout_0 = A1L81Q & (!A1L21);
A1L61 = CARRY(A1L61_cout_0);

--A1L71 is fifo_data[2]~101COUT1_127 at LC_X2_Y9_N2
--operation mode is arithmetic

A1L71_cout_1 = A1L81Q & (!A1L31);
A1L71 = CARRY(A1L71_cout_1);


--A1L22Q is fifo_data[3]~reg0 at LC_X2_Y9_N3
--operation mode is arithmetic

A1L22Q_lut_out = A1L22Q $ A1L61;
A1L22Q = DFFEAS(A1L22Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );

--A1L02 is fifo_data[3]~105 at LC_X2_Y9_N3
--operation mode is arithmetic

A1L02_cout_0 = !A1L61 # !A1L22Q;
A1L02 = CARRY(A1L02_cout_0);

--A1L12 is fifo_data[3]~105COUT1 at LC_X2_Y9_N3
--operation mode is arithmetic

A1L12_cout_1 = !A1L71 # !A1L22Q;
A1L12 = CARRY(A1L12_cout_1);


--A1L72Q is fifo_data[4]~reg0 at LC_X2_Y9_N4
--operation mode is arithmetic

A1L72Q_lut_out = A1L72Q $ !A1L02;
A1L72Q = DFFEAS(A1L72Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );

--A1L42 is fifo_data[4]~109 at LC_X2_Y9_N4
--operation mode is arithmetic

A1L42 = A1L52;


--A1L13Q is fifo_data[5]~reg0 at LC_X2_Y9_N5
--operation mode is arithmetic

A1L13Q_carry_eqn = (!A1L42 & GND) # (A1L42 & VCC);
A1L13Q_lut_out = A1L13Q $ (A1L13Q_carry_eqn);
A1L13Q = DFFEAS(A1L13Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );

--A1L92 is fifo_data[5]~113 at LC_X2_Y9_N5
--operation mode is arithmetic

A1L92_cout_0 = !A1L42 # !A1L13Q;
A1L92 = CARRY(A1L92_cout_0);

--A1L03 is fifo_data[5]~113COUT1_128 at LC_X2_Y9_N5
--operation mode is arithmetic

A1L03_cout_1 = !A1L42 # !A1L13Q;
A1L03 = CARRY(A1L03_cout_1);


--A1L53Q is fifo_data[6]~reg0 at LC_X2_Y9_N6
--operation mode is arithmetic

A1L53Q_carry_eqn = (!A1L42 & A1L92) # (A1L42 & A1L03);
A1L53Q_lut_out = A1L53Q $ (!A1L53Q_carry_eqn);
A1L53Q = DFFEAS(A1L53Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );

--A1L33 is fifo_data[6]~117 at LC_X2_Y9_N6
--operation mode is arithmetic

A1L33_cout_0 = A1L53Q & (!A1L92);
A1L33 = CARRY(A1L33_cout_0);

--A1L43 is fifo_data[6]~117COUT1_129 at LC_X2_Y9_N6
--operation mode is arithmetic

A1L43_cout_1 = A1L53Q & (!A1L03);
A1L43 = CARRY(A1L43_cout_1);


--A1L83Q is fifo_data[7]~reg0 at LC_X2_Y9_N7
--operation mode is normal

A1L83Q_carry_eqn = (!A1L42 & A1L33) # (A1L42 & A1L43);
A1L83Q_lut_out = A1L83Q $ (A1L83Q_carry_eqn);
A1L83Q = DFFEAS(A1L83Q_lut_out, !GLOBAL(clkin), VCC, , A1L73, VCC, !GLOBAL(rst), , );


--STATE.WRITE_1 is STATE.WRITE_1 at LC_X2_Y9_N8
--operation mode is normal

STATE.WRITE_1_lut_out = STATE.WRITE_2 # !fifo_full & STATE.WRITE_1 # !STATE.IDLE;
STATE.WRITE_1 = DFFEAS(STATE.WRITE_1_lut_out, !GLOBAL(clkin), GLOBAL(rst), , , , , , );


--clkin is clkin at LC_X19_Y10_N2
--operation mode is normal

clkin_lut_out = !clkin;
clkin = DFFEAS(clkin_lut_out, clk, GLOBAL(rst), , , , , , );


--A1L73 is fifo_data[7]~8 at LC_X2_Y9_N9
--operation mode is normal

A1L73 = fifo_full & (STATE.WRITE_1);

--STATE.WRITE_2 is STATE.WRITE_2 at LC_X2_Y9_N9
--operation mode is normal

STATE.WRITE_2 = DFFEAS(A1L73, !GLOBAL(clkin), GLOBAL(rst), , , , , , );


--STATE.IDLE is STATE.IDLE at LC_X1_Y9_N2
--operation mode is normal

STATE.IDLE_lut_out = STATE.WRITE_1 # STATE.WRITE_2 # !STATE.IDLE;
STATE.IDLE = DFFEAS(STATE.IDLE_lut_out, !GLOBAL(clkin), GLOBAL(rst), , , , , , );


--fifo_pf is fifo_pf at PIN_55
--operation mode is input

fifo_pf = INPUT();


--fifo_empty is fifo_empty at PIN_53
--operation mode is input

fifo_empty = INPUT();


--rst is rst at PIN_131
--operation mode is input

rst = INPUT();


--fifo_full is fifo_full at PIN_54
--operation mode is input

fifo_full = INPUT();


--clk is clk at PIN_153
--operation mode is input

clk = INPUT();


--fifo_wr is fifo_wr at PIN_56
--operation mode is output

fifo_wr = OUTPUT(!A1L44Q);


--fifo_rd is fifo_rd at PIN_57
--operation mode is output

fifo_rd = OUTPUT(VCC);


--fifo_data[0] is fifo_data[0] at PIN_58
--operation mode is output

fifo_data[0] = OUTPUT(A1L01Q);


--fifo_data[1] is fifo_data[1] at PIN_59
--operation mode is output

fifo_data[1] = OUTPUT(A1L41Q);


--fifo_data[2] is fifo_data[2] at PIN_60
--operation mode is output

fifo_data[2] = OUTPUT(A1L81Q);


--fifo_data[3] is fifo_data[3] at PIN_61
--operation mode is output

fifo_data[3] = OUTPUT(A1L22Q);


--fifo_data[4] is fifo_data[4] at PIN_62
--operation mode is output

fifo_data[4] = OUTPUT(A1L72Q);


--fifo_data[5] is fifo_data[5] at PIN_63
--operation mode is output

fifo_data[5] = OUTPUT(A1L13Q);


--fifo_data[6] is fifo_data[6] at PIN_64
--operation mode is output

fifo_data[6] = OUTPUT(A1L53Q);


--fifo_data[7] is fifo_data[7] at PIN_65
--operation mode is output

fifo_data[7] = OUTPUT(A1L83Q);