fpga2pc.map.rpt

usb芯片cy7c68013从fpga中读入数据的演示程序

; Total logic elements              ; 14      ;
; Total combinational functions     ; 11      ;
;     -- Total 4-input functions    ; 1       ;
;     -- Total 3-input functions    ; 1       ;
;     -- Total 2-input functions    ; 1       ;
;     -- Total 1-input functions    ; 8       ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 13      ;
; Total logic cells in carry chains ; 8       ;
; I/O pins                          ; 15      ;
; Maximum fan-out node              ; clkin   ;
; Maximum fan-out                   ; 13      ;
; Total fan-out                     ; 70      ;
; Average fan-out                   ; 2.41    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |fpga2pc                   ; 14 (14)     ; 13           ; 0           ; 15   ; 0            ; 1 (1)        ; 3 (3)             ; 10 (10)          ; 8 (8)           ; |fpga2pc            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; State Machine - |fpga2pc|STATE                             ;
+---------------+------------+---------------+---------------+
; Name          ; STATE.IDLE ; STATE.WRITE_2 ; STATE.WRITE_1 ;
+---------------+------------+---------------+---------------+
; STATE.IDLE    ; 0          ; 0             ; 0             ;
; STATE.WRITE_2 ; 1          ; 1             ; 0             ;
; STATE.WRITE_1 ; 1          ; 0             ; 1             ;
+---------------+------------+---------------+---------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 13    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 5     ;
; Number of registers using Asynchronous Load  ; 8     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; fifo_wr~reg0                           ; 1       ;
; clkin                                  ; 13      ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |fpga2pc ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; IDLE           ; 000   ; Binary                                         ;
; WRITE_1        ; 001   ; Binary                                         ;
; WRITE_2        ; 010   ; Binary                                         ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/code/EP1C6/T2_USB_IN/Proj/fpga2pc.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Thu Feb 23 15:01:13 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USB_IN -c fpga2pc
Warning: Verilog Module Declaration warning at fpga2pc.v(11): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "fpga2pc"
Info: Found 1 design units, including 1 entities, in source file ../Src/fpga2pc.v
    Info: Found entity 1: fpga2pc
Info: Elaborating entity "fpga2pc" for the top level hierarchy
Warning: Verilog HDL assignment warning at fpga2pc.v(44): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at fpga2pc.v(56): variable "fifo_full" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at fpga2pc.v(83): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fpga2pc.v(84): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fpga2pc.v(88): truncated value with size 32 to match size of target (8)
Info: Power-up level of register "fifo_rd~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "fifo_rd~reg0" with stuck data_in port to stuck value VCC
Info: State machine "|fpga2pc|STATE" contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|fpga2pc|STATE"
Info: Encoding result for state machine "|fpga2pc|STATE"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "STATE.IDLE"
        Info: Encoded state bit "STATE.WRITE_2"
        Info: Encoded state bit "STATE.WRITE_1"
    Info: State "|fpga2pc|STATE.IDLE" uses code string "000"
    Info: State "|fpga2pc|STATE.WRITE_2" uses code string "110"
    Info: State "|fpga2pc|STATE.WRITE_1" uses code string "101"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "fifo_rd" stuck at VCC
Info: Registers with preset signals will power-up high
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "fifo_pf"
    Warning: No output dependent on input pin "fifo_empty"
Info: Implemented 29 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 10 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Thu Feb 23 15:01:14 2006
    Info: Elapsed time: 00:00:02