fpga2pc.map.eqn

usb芯片cy7c68013从fpga中读入数据的演示程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L63Q is fifo_wr~reg0
--operation mode is normal

A1L63Q_lut_out = STATE.WRITE_1;
A1L63Q = DFFEAS(A1L63Q_lut_out, !clkin, rst, , , , , , );


--A1L9Q is fifo_data[0]~reg0
--operation mode is arithmetic

A1L9Q_lut_out = !A1L9Q;
A1L9Q = DFFEAS(A1L9Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );

--A1L8 is fifo_data[0]~93
--operation mode is arithmetic

A1L8 = CARRY(A1L9Q);


--A1L21Q is fifo_data[1]~reg0
--operation mode is arithmetic

A1L21Q_carry_eqn = A1L8;
A1L21Q_lut_out = A1L21Q $ (A1L21Q_carry_eqn);
A1L21Q = DFFEAS(A1L21Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );

--A1L11 is fifo_data[1]~97
--operation mode is arithmetic

A1L11 = CARRY(!A1L8 # !A1L21Q);


--A1L51Q is fifo_data[2]~reg0
--operation mode is arithmetic

A1L51Q_carry_eqn = A1L11;
A1L51Q_lut_out = A1L51Q $ (!A1L51Q_carry_eqn);
A1L51Q = DFFEAS(A1L51Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );

--A1L41 is fifo_data[2]~101
--operation mode is arithmetic

A1L41 = CARRY(A1L51Q & (!A1L11));


--A1L81Q is fifo_data[3]~reg0
--operation mode is arithmetic

A1L81Q_carry_eqn = A1L41;
A1L81Q_lut_out = A1L81Q $ (A1L81Q_carry_eqn);
A1L81Q = DFFEAS(A1L81Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );

--A1L71 is fifo_data[3]~105
--operation mode is arithmetic

A1L71 = CARRY(!A1L41 # !A1L81Q);


--A1L12Q is fifo_data[4]~reg0
--operation mode is arithmetic

A1L12Q_carry_eqn = A1L71;
A1L12Q_lut_out = A1L12Q $ (!A1L12Q_carry_eqn);
A1L12Q = DFFEAS(A1L12Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );

--A1L02 is fifo_data[4]~109
--operation mode is arithmetic

A1L02 = CARRY(A1L12Q & (!A1L71));


--A1L42Q is fifo_data[5]~reg0
--operation mode is arithmetic

A1L42Q_carry_eqn = A1L02;
A1L42Q_lut_out = A1L42Q $ (A1L42Q_carry_eqn);
A1L42Q = DFFEAS(A1L42Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );

--A1L32 is fifo_data[5]~113
--operation mode is arithmetic

A1L32 = CARRY(!A1L02 # !A1L42Q);


--A1L72Q is fifo_data[6]~reg0
--operation mode is arithmetic

A1L72Q_carry_eqn = A1L32;
A1L72Q_lut_out = A1L72Q $ (!A1L72Q_carry_eqn);
A1L72Q = DFFEAS(A1L72Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );

--A1L62 is fifo_data[6]~117
--operation mode is arithmetic

A1L62 = CARRY(A1L72Q & (!A1L32));


--A1L03Q is fifo_data[7]~reg0
--operation mode is normal

A1L03Q_carry_eqn = A1L62;
A1L03Q_lut_out = A1L03Q $ (A1L03Q_carry_eqn);
A1L03Q = DFFEAS(A1L03Q_lut_out, !clkin, VCC, , A1L92, VCC, !rst, , );


--STATE.WRITE_1 is STATE.WRITE_1
--operation mode is normal

STATE.WRITE_1_lut_out = STATE.WRITE_2 # STATE.WRITE_1 & !fifo_full # !STATE.IDLE;
STATE.WRITE_1 = DFFEAS(STATE.WRITE_1_lut_out, !clkin, rst, , , , , , );


--clkin is clkin
--operation mode is normal

clkin_lut_out = !clkin;
clkin = DFFEAS(clkin_lut_out, clk, rst, , , , , , );


--A1L92 is fifo_data[7]~8
--operation mode is normal

A1L92 = STATE.WRITE_1 & fifo_full;


--STATE.WRITE_2 is STATE.WRITE_2
--operation mode is normal

STATE.WRITE_2_lut_out = A1L92;
STATE.WRITE_2 = DFFEAS(STATE.WRITE_2_lut_out, !clkin, rst, , , , , , );


--STATE.IDLE is STATE.IDLE
--operation mode is normal

STATE.IDLE_lut_out = STATE.WRITE_1 # STATE.WRITE_2 # !STATE.IDLE;
STATE.IDLE = DFFEAS(STATE.IDLE_lut_out, !clkin, rst, , , , , , );


--fifo_pf is fifo_pf
--operation mode is input

fifo_pf = INPUT();


--fifo_empty is fifo_empty
--operation mode is input

fifo_empty = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--fifo_full is fifo_full
--operation mode is input

fifo_full = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--fifo_wr is fifo_wr
--operation mode is output

fifo_wr = OUTPUT(!A1L63Q);


--fifo_rd is fifo_rd
--operation mode is output

fifo_rd = OUTPUT(VCC);


--fifo_data[0] is fifo_data[0]
--operation mode is output

fifo_data[0] = OUTPUT(A1L9Q);


--fifo_data[1] is fifo_data[1]
--operation mode is output

fifo_data[1] = OUTPUT(A1L21Q);


--fifo_data[2] is fifo_data[2]
--operation mode is output

fifo_data[2] = OUTPUT(A1L51Q);


--fifo_data[3] is fifo_data[3]
--operation mode is output

fifo_data[3] = OUTPUT(A1L81Q);


--fifo_data[4] is fifo_data[4]
--operation mode is output

fifo_data[4] = OUTPUT(A1L12Q);


--fifo_data[5] is fifo_data[5]
--operation mode is output

fifo_data[5] = OUTPUT(A1L42Q);


--fifo_data[6] is fifo_data[6]
--operation mode is output

fifo_data[6] = OUTPUT(A1L72Q);


--fifo_data[7] is fifo_data[7]
--operation mode is output

fifo_data[7] = OUTPUT(A1L03Q);