serial.map.summary

来自「串口通讯 verilog CPLD EPM1270 源代码」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Sat Feb 18 13:25:16 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : serial
Top-level Entity Name : serial
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 188
Total pins : 22
Total virtual pins : 0
UFM blocks : 0