uart.map.qmsg

串口实验

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 12:31:58 2006 " "Info: Processing started: Sat Feb 18 12:31:58 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UART -c UART " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART -c UART" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UART.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART-arch " "Info: Found design unit 1: UART-arch" {  } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" {  } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UART " "Info: Elaborating entity \"UART\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "txd_buf\[7\] data_in GND " "Warning: Reduced register \"txd_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 50 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "en GND " "Warning: Pin \"en\" stuck at GND" {  } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[0\] VCC " "Warning: Pin \"seg_data\[0\]\" stuck at VCC" {  } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 26 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 48 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "226 " "Info: Implemented 226 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "212 " "Info: Implemented 212 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 12:32:06 2006 " "Info: Processing ended: Sat Feb 18 12:32:06 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}