uart.tan.qmsg

串口实验

{ "Info" "ITDB_TH_RESULT" "rxd_reg1 rxd clk 5.925 ns register " "Info: th for register \"rxd_reg1\" (data pin = \"rxd\", clock pin = \"clk\") is 5.925 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.848 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 39 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 39; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { clk } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(1.294 ns) 7.096 ns clkbaud8x 2 REG LC_X8_Y4_N9 40 " "Info: 2: + IC(4.670 ns) + CELL(1.294 ns) = 7.096 ns; Loc. = LC_X8_Y4_N9; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.964 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.834 ns) + CELL(0.918 ns) 11.848 ns rxd_reg1 3 REG LC_X14_Y6_N9 2 " "Info: 3: + IC(3.834 ns) + CELL(0.918 ns) = 11.848 ns; Loc. = LC_X14_Y6_N9; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "4.752 ns" { clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 28.22 % " "Info: Total cell delay = 3.344 ns ( 28.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.504 ns 71.78 % " "Info: Total interconnect delay = 8.504 ns ( 71.78 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "11.848 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.848 ns" { clk clk~combout clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 4.670ns 3.834ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.144 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rxd 1 PIN PIN_77 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_77; Fanout = 1; PIN Node = 'rxd'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { rxd } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.732 ns) + CELL(0.280 ns) 6.144 ns rxd_reg1 2 REG LC_X14_Y6_N9 2 " "Info: 2: + IC(4.732 ns) + CELL(0.280 ns) = 6.144 ns; Loc. = LC_X14_Y6_N9; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.012 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns 22.98 % " "Info: Total cell delay = 1.412 ns ( 22.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.732 ns 77.02 % " "Info: Total interconnect delay = 4.732 ns ( 77.02 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "6.144 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.144 ns" { rxd rxd~combout rxd_reg1 } { 0.000ns 0.000ns 4.732ns } { 0.000ns 1.132ns 0.280ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "11.848 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.848 ns" { clk clk~combout clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 4.670ns 3.834ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "6.144 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.144 ns" { rxd rxd~combout rxd_reg1 } { 0.000ns 0.000ns 4.732ns } { 0.000ns 1.132ns 0.280ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 12:32:23 2006 " "Info: Processing ended: Sat Feb 18 12:32:23 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}