📄 uart.tan.qmsg
字号:
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "key_entry1 key_entry2 clk 2.021 ns " "Info: Found hold time violation between source pin or register \"key_entry1\" and destination pin or register \"key_entry2\" for clock \"clk\" (Hold time is 2.021 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.128 ns + Largest " "Info: + Largest clock skew is 5.128 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.848 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 39 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 39; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { clk } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(1.294 ns) 7.096 ns clkbaud8x 2 REG LC_X8_Y4_N9 40 " "Info: 2: + IC(4.670 ns) + CELL(1.294 ns) = 7.096 ns; Loc. = LC_X8_Y4_N9; Fanout = 40; REG Node = 'clkbaud8x'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.964 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.834 ns) + CELL(0.918 ns) 11.848 ns key_entry2 3 REG LC_X13_Y3_N0 18 " "Info: 3: + IC(3.834 ns) + CELL(0.918 ns) = 11.848 ns; Loc. = LC_X13_Y3_N0; Fanout = 18; REG Node = 'key_entry2'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "4.752 ns" { clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 55 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 28.22 % " "Info: Total cell delay = 3.344 ns ( 28.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.504 ns 71.78 % " "Info: Total interconnect delay = 8.504 ns ( 71.78 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "11.848 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.848 ns" { clk clk~combout clkbaud8x key_entry2 } { 0.0ns 0.0ns 4.67ns 3.834ns } { 0.0ns 1.132ns 1.294ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.720 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 39 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 39; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { clk } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns key_entry1 2 REG LC_X14_Y3_N2 4 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X14_Y3_N2; Fanout = 4; REG Node = 'key_entry1'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.588 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "6.720 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout key_entry1 } { 0.0ns 0.0ns 4.67ns } { 0.0ns 1.132ns 0.918ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "11.848 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.848 ns" { clk clk~combout clkbaud8x key_entry2 } { 0.0ns 0.0ns 4.67ns 3.834ns } { 0.0ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "6.720 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout key_entry1 } { 0.0ns 0.0ns 4.67ns } { 0.0ns 1.132ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.952 ns - Shortest register register " "Info: - Shortest register to register delay is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_entry1 1 REG LC_X14_Y3_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y3_N2; Fanout = 4; REG Node = 'key_entry1'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { key_entry1 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.672 ns) + CELL(0.280 ns) 2.952 ns key_entry2 2 REG LC_X13_Y3_N0 18 " "Info: 2: + IC(2.672 ns) + CELL(0.280 ns) = 2.952 ns; Loc. = LC_X13_Y3_N0; Fanout = 18; REG Node = 'key_entry2'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "2.952 ns" { key_entry1 key_entry2 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 55 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns 9.49 % " "Info: Total cell delay = 0.280 ns ( 9.49 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.672 ns 90.51 % " "Info: Total interconnect delay = 2.672 ns ( 90.51 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "2.952 ns" { key_entry1 key_entry2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.952 ns" { key_entry1 key_entry2 } { 0.0ns 2.672ns } { 0.0ns 0.28ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 55 -1 0 } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "11.848 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.848 ns" { clk clk~combout clkbaud8x key_entry2 } { 0.0ns 0.0ns 4.67ns 3.834ns } { 0.0ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "6.720 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout key_entry1 } { 0.0ns 0.0ns 4.67ns } { 0.0ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "2.952 ns" { key_entry1 key_entry2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.952 ns" { key_entry1 key_entry2 } { 0.0ns 2.672ns } { 0.0ns 0.28ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "start_delaycnt key_input clk -1.009 ns register " "Info: tsu for register \"start_delaycnt\" (data pin = \"key_input\", clock pin = \"clk\") is -1.009 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.378 ns + Longest pin register " "Info: + Longest pin to register delay is 5.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns key_input 1 PIN PIN_72 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_72; Fanout = 2; PIN Node = 'key_input'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { key_input } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.214 ns) + CELL(0.200 ns) 3.546 ns start_delaycnt~225 2 COMB LC_X16_Y2_N0 1 " "Info: 2: + IC(2.214 ns) + CELL(0.200 ns) = 3.546 ns; Loc. = LC_X16_Y2_N0; Fanout = 1; COMB Node = 'start_delaycnt~225'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "2.414 ns" { key_input start_delaycnt~225 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.051 ns start_delaycnt~226 3 COMB LC_X16_Y2_N1 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 4.051 ns; Loc. = LC_X16_Y2_N1; Fanout = 1; COMB Node = 'start_delaycnt~226'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "0.505 ns" { start_delaycnt~225 start_delaycnt~226 } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.591 ns) 5.378 ns start_delaycnt 4 REG LC_X16_Y2_N5 21 " "Info: 4: + IC(0.736 ns) + CELL(0.591 ns) = 5.378 ns; Loc. = LC_X16_Y2_N5; Fanout = 21; REG Node = 'start_delaycnt'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "1.327 ns" { start_delaycnt~226 start_delaycnt } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.123 ns 39.48 % " "Info: Total cell delay = 2.123 ns ( 39.48 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.255 ns 60.52 % " "Info: Total interconnect delay = 3.255 ns ( 60.52 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.378 ns" { key_input start_delaycnt~225 start_delaycnt~226 start_delaycnt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.378 ns" { key_input key_input~combout start_delaycnt~225 start_delaycnt~226 start_delaycnt } { 0.000ns 0.000ns 2.214ns 0.305ns 0.736ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.591ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.720 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 39 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 39; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { clk } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.918 ns) 6.720 ns start_delaycnt 2 REG LC_X16_Y2_N5 21 " "Info: 2: + IC(4.670 ns) + CELL(0.918 ns) = 6.720 ns; Loc. = LC_X16_Y2_N5; Fanout = 21; REG Node = 'start_delaycnt'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.588 ns" { clk start_delaycnt } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 53 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.51 % " "Info: Total cell delay = 2.050 ns ( 30.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns 69.49 % " "Info: Total interconnect delay = 4.670 ns ( 69.49 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "6.720 ns" { clk start_delaycnt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout start_delaycnt } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.378 ns" { key_input start_delaycnt~225 start_delaycnt~226 start_delaycnt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.378 ns" { key_input key_input~combout start_delaycnt~225 start_delaycnt~226 start_delaycnt } { 0.000ns 0.000ns 2.214ns 0.305ns 0.736ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.591ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "6.720 ns" { clk start_delaycnt } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.720 ns" { clk clk~combout start_delaycnt } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.132ns 0.918ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[1\] rxd_buf\[5\] 22.933 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[1\]\" through register \"rxd_buf\[5\]\" is 22.933 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.848 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 39 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 39; CLK Node = 'clk'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { clk } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(1.294 ns) 7.096 ns clkbaud8x 2 REG LC_X8_Y4_N9 40 " "Info: 2: + IC(4.670 ns) + CELL(1.294 ns) = 7.096 ns; Loc. = LC_X8_Y4_N9; Fanout = 40; REG Node = 'clkbaud8x'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "5.964 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.834 ns) + CELL(0.918 ns) 11.848 ns rxd_buf\[5\] 3 REG LC_X14_Y9_N6 14 " "Info: 3: + IC(3.834 ns) + CELL(0.918 ns) = 11.848 ns; Loc. = LC_X14_Y9_N6; Fanout = 14; REG Node = 'rxd_buf\[5\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "4.752 ns" { clkbaud8x rxd_buf[5] } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns 28.22 % " "Info: Total cell delay = 3.344 ns ( 28.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.504 ns 71.78 % " "Info: Total interconnect delay = 8.504 ns ( 71.78 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "11.848 ns" { clk clkbaud8x rxd_buf[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.848 ns" { clk clk~combout clkbaud8x rxd_buf[5] } { 0.000ns 0.000ns 4.670ns 3.834ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.709 ns + Longest register pin " "Info: + Longest register to pin delay is 10.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd_buf\[5\] 1 REG LC_X14_Y9_N6 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y9_N6; Fanout = 14; REG Node = 'rxd_buf\[5\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "" { rxd_buf[5] } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.957 ns) + CELL(0.914 ns) 1.871 ns reduce_or~2715 2 COMB LC_X14_Y9_N5 1 " "Info: 2: + IC(0.957 ns) + CELL(0.914 ns) = 1.871 ns; Loc. = LC_X14_Y9_N5; Fanout = 1; COMB Node = 'reduce_or~2715'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "1.871 ns" { rxd_buf[5] reduce_or~2715 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.914 ns) 4.006 ns reduce_or~2716 3 COMB LC_X14_Y9_N8 1 " "Info: 3: + IC(1.221 ns) + CELL(0.914 ns) = 4.006 ns; Loc. = LC_X14_Y9_N8; Fanout = 1; COMB Node = 'reduce_or~2716'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "2.135 ns" { reduce_or~2715 reduce_or~2716 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.200 ns) 5.377 ns reduce_or~2718 4 COMB LC_X14_Y9_N3 1 " "Info: 4: + IC(1.171 ns) + CELL(0.200 ns) = 5.377 ns; Loc. = LC_X14_Y9_N3; Fanout = 1; COMB Node = 'reduce_or~2718'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "1.371 ns" { reduce_or~2716 reduce_or~2718 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.882 ns reduce_or~2719 5 COMB LC_X14_Y9_N4 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.882 ns; Loc. = LC_X14_Y9_N4; Fanout = 1; COMB Node = 'reduce_or~2719'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "0.505 ns" { reduce_or~2718 reduce_or~2719 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.505 ns) + CELL(2.322 ns) 10.709 ns seg_data\[1\] 6 PIN PIN_119 0 " "Info: 6: + IC(2.505 ns) + CELL(2.322 ns) = 10.709 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'seg_data\[1\]'" { } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "4.827 ns" { reduce_or~2719 seg_data[1] } "NODE_NAME" } "" } } { "UART.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/UART.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.550 ns 42.49 % " "Info: Total cell delay = 4.550 ns ( 42.49 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.159 ns 57.51 % " "Info: Total interconnect delay = 6.159 ns ( 57.51 % )" { } { } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "10.709 ns" { rxd_buf[5] reduce_or~2715 reduce_or~2716 reduce_or~2718 reduce_or~2719 seg_data[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.709 ns" { rxd_buf[5] reduce_or~2715 reduce_or~2716 reduce_or~2718 reduce_or~2719 seg_data[1] } { 0.000ns 0.957ns 1.221ns 1.171ns 0.305ns 2.505ns } { 0.000ns 0.914ns 0.914ns 0.200ns 0.200ns 2.322ns } } } } 0} } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "11.848 ns" { clk clkbaud8x rxd_buf[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.848 ns" { clk clk~combout clkbaud8x rxd_buf[5] } { 0.000ns 0.000ns 4.670ns 3.834ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART_cmp.qrpt" Compiler "UART" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/db/UART.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/UART/" "" "10.709 ns" { rxd_buf[5] reduce_or~2715 reduce_or~2716 reduce_or~2718 reduce_or~2719 seg_data[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.709 ns" { rxd_buf[5] reduce_or~2715 reduce_or~2716 reduce_or~2718 reduce_or~2719 seg_data[1] } { 0.000ns 0.957ns 1.221ns 1.171ns 0.305ns 2.505ns } { 0.000ns 0.914ns 0.914ns 0.200ns 0.200ns 2.322ns } } } } 0}
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