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除法器实验 verilog CPLD EPM1270 源代码

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L1 is LessThan~176
--operation mode is normal

A1L1 = b[0] & (!a[1]);


--A1L2 is LessThan~177
--operation mode is normal

A1L2 = A1L1 # b[2] # b[1] & !a[2];


--A1L3 is LessThan~178
--operation mode is normal

A1L3 = b[1] # b[2] # b[0] & !a[2];


--A1L12 is c_tmp[0]~451
--operation mode is normal

A1L12 = a[0] & (a[2] # !b[2]) # !a[0] & b[1] & !b[2] & a[2];


--A1L22 is c_tmp[0]~452
--operation mode is normal

A1L22 = b[1] & (b[2] $ a[2]) # !b[1] & (b[2] & a[2]);


--A1L32 is c_tmp[0]~453
--operation mode is normal

A1L32 = b[1] & (A1L12 # !b[0] & !A1L22) # !b[1] & b[0] & !A1L12 & A1L22;


--A1L42 is c_tmp[0]~454
--operation mode is normal

A1L42 = b[0] & A1L12 & (A1L22 # !b[1]) # !b[0] & !b[1] & (A1L22);


--A1L52 is c_tmp[0]~455
--operation mode is normal

A1L52 = A1L42 $ (!A1L32 # !a[1]);


--A1L73 is reduce_or~733
--operation mode is normal

A1L73 = A1L2 & A1L3 # !A1L2 & !A1L3 & (!A1L52);


--A1L83 is reduce_or~734
--operation mode is normal

A1L83 = A1L2 & (A1L52 # !A1L3) # !A1L2 & A1L52 & (!A1L3);


--A1L93 is reduce_or~735
--operation mode is normal

A1L93 = !b[1] & !b[2];


--A1L04 is reduce_or~736
--operation mode is normal

A1L04 = a[2] & A1L1 & A1L93 # !A1L52;


--A1L14 is reduce_or~737
--operation mode is normal

A1L14 = A1L2 & (A1L3 $ A1L52) # !A1L2 & (!A1L3 & !A1L52);


--A1L24 is reduce_or~738
--operation mode is normal

A1L24 = A1L3 # A1L2 $ !A1L52;


--A1L34 is reduce_or~739
--operation mode is normal

A1L34 = A1L2 & (A1L3 $ A1L52);


--A1L53 is reduce_or~729
--operation mode is normal

A1L53 = !b[1] & (a[1] & !a[0] # !b[0]);


--A1L63 is reduce_or~730
--operation mode is normal

A1L63 = b[0] $ (!b[1] # !a[1]);


--A1L44 is reduce_or~740
--operation mode is normal

A1L44 = !b[2] & (a[2] & (A1L63) # !a[2] & A1L53);


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(A1L73);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(!A1L83);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L04);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(A1L14);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(A1L44);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(!A1L24);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L34);


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(VCC);