div.tan.qmsg

除法器实验 verilog CPLD EPM1270 源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 13:54:42 2006 " "Info: Processing started: Sat Feb 18 13:54:42 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off div -c div --speed=5 " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off div -c div --speed=5" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] c\[2\] 13.596 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"c\[2\]\" is 13.596 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[0\] 1 PIN PIN_71 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 2; PIN Node = 'a\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" Compiler "div" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/" "" "" { a[0] } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/div.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.528 ns) + CELL(0.914 ns) 5.574 ns c_tmp\[0\]~451 2 COMB LC_X13_Y8_N5 2 " "Info: 2: + IC(3.528 ns) + CELL(0.914 ns) = 5.574 ns; Loc. = LC_X13_Y8_N5; Fanout = 2; COMB Node = 'c_tmp\[0\]~451'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" Compiler "div" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/" "" "4.442 ns" { a[0] c_tmp[0]~451 } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/div.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.511 ns) 6.857 ns c_tmp\[0\]~454 3 COMB LC_X13_Y8_N1 1 " "Info: 3: + IC(0.772 ns) + CELL(0.511 ns) = 6.857 ns; Loc. = LC_X13_Y8_N1; Fanout = 1; COMB Node = 'c_tmp\[0\]~454'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" Compiler "div" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/" "" "1.283 ns" { c_tmp[0]~451 c_tmp[0]~454 } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/div.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(0.200 ns) 7.771 ns c_tmp\[0\]~455 4 COMB LC_X13_Y8_N8 6 " "Info: 4: + IC(0.714 ns) + CELL(0.200 ns) = 7.771 ns; Loc. = LC_X13_Y8_N8; Fanout = 6; COMB Node = 'c_tmp\[0\]~455'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" Compiler "div" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/" "" "0.914 ns" { c_tmp[0]~454 c_tmp[0]~455 } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/div.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.200 ns) 8.745 ns reduce_or~734 5 COMB LC_X13_Y8_N2 1 " "Info: 5: + IC(0.774 ns) + CELL(0.200 ns) = 8.745 ns; Loc. = LC_X13_Y8_N2; Fanout = 1; COMB Node = 'reduce_or~734'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" Compiler "div" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/" "" "0.974 ns" { c_tmp[0]~455 reduce_or~734 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.529 ns) + CELL(2.322 ns) 13.596 ns c\[2\] 6 PIN PIN_117 0 " "Info: 6: + IC(2.529 ns) + CELL(2.322 ns) = 13.596 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" Compiler "div" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/" "" "4.851 ns" { reduce_or~734 c[2] } "NODE_NAME" } "" } } { "div.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/div.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.279 ns 38.83 % " "Info: Total cell delay = 5.279 ns ( 38.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.317 ns 61.17 % " "Info: Total interconnect delay = 8.317 ns ( 61.17 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div_cmp.qrpt" Compiler "div" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/db/div.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/除法器/" "" "13.596 ns" { a[0] c_tmp[0]~451 c_tmp[0]~454 c_tmp[0]~455 reduce_or~734 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.596 ns" { a[0] a[0]~combout c_tmp[0]~451 c_tmp[0]~454 c_tmp[0]~455 reduce_or~734 c[2] } { 0.000ns 0.000ns 3.528ns 0.772ns 0.714ns 0.774ns 2.529ns } { 0.000ns 1.132ns 0.914ns 0.511ns 0.200ns 0.200ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:54:44 2006 " "Info: Processing ended: Sat Feb 18 13:54:44 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}