📄 decl7s.tan.rpt
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Timing Analyzer report for DECL7S
Wed Oct 29 10:43:51 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.307 ns ; A[2] ; LED7S[4] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----------+
; N/A ; None ; 11.307 ns ; A[2] ; LED7S[4] ;
; N/A ; None ; 11.178 ns ; A[0] ; LED7S[4] ;
; N/A ; None ; 11.092 ns ; A[2] ; LED7S[5] ;
; N/A ; None ; 11.087 ns ; A[2] ; LED7S[2] ;
; N/A ; None ; 11.082 ns ; A[3] ; LED7S[4] ;
; N/A ; None ; 11.067 ns ; A[1] ; LED7S[4] ;
; N/A ; None ; 10.993 ns ; A[2] ; LED7S[3] ;
; N/A ; None ; 10.993 ns ; A[2] ; LED7S[0] ;
; N/A ; None ; 10.976 ns ; A[0] ; LED7S[2] ;
; N/A ; None ; 10.973 ns ; A[0] ; LED7S[5] ;
; N/A ; None ; 10.890 ns ; A[0] ; LED7S[3] ;
; N/A ; None ; 10.878 ns ; A[0] ; LED7S[0] ;
; N/A ; None ; 10.865 ns ; A[3] ; LED7S[5] ;
; N/A ; None ; 10.863 ns ; A[3] ; LED7S[2] ;
; N/A ; None ; 10.862 ns ; A[1] ; LED7S[2] ;
; N/A ; None ; 10.859 ns ; A[1] ; LED7S[5] ;
; N/A ; None ; 10.775 ns ; A[1] ; LED7S[3] ;
; N/A ; None ; 10.768 ns ; A[3] ; LED7S[3] ;
; N/A ; None ; 10.766 ns ; A[3] ; LED7S[0] ;
; N/A ; None ; 10.764 ns ; A[1] ; LED7S[0] ;
; N/A ; None ; 10.710 ns ; A[2] ; LED7S[6] ;
; N/A ; None ; 10.677 ns ; A[2] ; LED7S[1] ;
; N/A ; None ; 10.584 ns ; A[0] ; LED7S[6] ;
; N/A ; None ; 10.555 ns ; A[0] ; LED7S[1] ;
; N/A ; None ; 10.483 ns ; A[3] ; LED7S[6] ;
; N/A ; None ; 10.470 ns ; A[1] ; LED7S[6] ;
; N/A ; None ; 10.450 ns ; A[3] ; LED7S[1] ;
; N/A ; None ; 10.441 ns ; A[1] ; LED7S[1] ;
+-------+-------------------+-----------------+------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed Oct 29 10:43:50 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DECL7S -c DECL7S --timing_analysis_only
Info: Longest tpd from source pin "A[2]" to destination pin "LED7S[4]" is 11.307 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_143; Fanout = 7; PIN Node = 'A[2]'
Info: 2: + IC(5.167 ns) + CELL(0.590 ns) = 7.232 ns; Loc. = LC_X2_Y11_N5; Fanout = 1; COMB Node = 'Mux2~3'
Info: 3: + IC(1.967 ns) + CELL(2.108 ns) = 11.307 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'LED7S[4]'
Info: Total cell delay = 4.173 ns ( 36.91 % )
Info: Total interconnect delay = 7.134 ns ( 63.09 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Oct 29 10:43:51 2008
Info: Elapsed time: 00:00:03
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