bcd_digit.vhd

基于Actel的VHDL编程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BCD_digit is
  port (clear_n : in std_logic;
        clock   : in std_logic;
        carry_in : in std_logic;    -- carry digit from previous 
        carry_out : out std_logic;    -- carry digit to next
        digit   : out std_logic_vector (3 downto 0)
        );
end;

architecture behave of BCD_digit is
  signal digit_int : std_logic_vector(3 downto 0);
begin

  step : process(clear_n, clock)
  begin
    if clear_n = '0' then
        digit_int <= (others => '0');
    elsif clock'event and clock='1' then
        case digit_int is
            when "0000" =>
                digit_int <= "000" & carry_in; 
            when "0001" =>
                digit_int <= "001" & carry_in;
            when "0010" =>
                digit_int <= "010" & carry_in;
            when "0011" =>
                digit_int <= "011" & carry_in;
            when "0100" =>
                digit_int <= "100" & carry_in;
            when "0101" =>
                digit_int <= "000" & carry_in;
            when "0110" =>
                digit_int <= "001" & carry_in;
            when "0111" =>
                digit_int <= "010" & carry_in;
            when "1000" =>
                digit_int <= "011" & carry_in;
            when "1001" =>
                digit_int <= "100" & carry_in;
            when others =>
                null;
        end case;
    end if;
  end process;

  digit <= digit_int;
  with digit_int select 
    carry_out <= '1' when  x"5" | x"6" | x"7" | x"8" | x"9",
                 '0' when others;
end;