📄 sequence_tp.v
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module sequence_tp; reg reset,clk,signalin; wire signalout; wire [2:0] state; parameter DELY=100; sequence_inspector mysequence(signalout,reset,clk,signalin); always #(DELY/2) clk=~clk; initial begin clk=0; reset=0; #DELY reset=1; #DELY reset=0; #DELY signalin=1; #DELY signalin=0; #DELY signalin=0; #DELY signalin=1; #DELY signalin=0; end initial begin $monitor($time,,,,, "clk=%d,reset=%d,signalin=%d,state=%d,signalout=%d",clk,reset,signalin,state,signalout); end endmodule
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