sequence_tp.v

来自「序列检测器可用于检测一组或多组二进制码组成的脉冲序列信号」· Verilog 代码 · 共 28 行

	module sequence_tp;
	reg reset,clk,signalin;
	wire signalout;
	wire [2:0] state;
	parameter DELY=100;
	
	sequence_inspector mysequence(signalout,reset,clk,signalin);
	always #(DELY/2) clk=~clk;
	initial
	  begin
	    clk=0;
	    reset=0;
	    #DELY reset=1;
	    #DELY reset=0;
	    #DELY signalin=1;
	    #DELY signalin=0;
	    #DELY signalin=0;
	    #DELY signalin=1;
	    #DELY signalin=0;

	  end 
  initial
  begin
  $monitor($time,,,,, "clk=%d,reset=%d,signalin=%d,state=%d,signalout=%d",clk,reset,signalin,state,signalout);
  end
  endmodule