📄 formatter.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity formatter is
Port (
reset_n : in std_logic;
clock : in std_logic;
format_select: in std_logic_vector (2 downto 0);
counts_in : in std_logic_vector (11 downto 0);
data_out : out std_logic_vector (63 downto 0)
);
end formatter ;
architecture behave of formatter is
component BCD_digit is
port (clear_n : in std_logic;
clock : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
digit : out std_logic_vector (3 downto 0)
);
end component;
signal counts_in_int: std_logic_vector (11 downto 0);
signal counts_in_int_int: std_logic_vector (11 downto 0);
signal scaled_input : std_logic_vector (15 downto 0);
signal BCD_input_reg : std_logic_vector (15 downto 0);
signal BCD_counts : std_logic_vector (15 downto 0);
signal BCD_counts_reg : std_logic_vector (15 downto 0);
signal BCD_char1 : std_logic_vector (3 downto 0);
signal BCD_char2 : std_logic_vector (3 downto 0);
signal BCD_char3 : std_logic_vector (3 downto 0);
signal BCD_char4 : std_logic_vector (3 downto 0);
signal carry_bits : std_logic_vector (4 downto 0);
signal BCD_shiftcount : std_logic_vector (4 downto 0);
signal BCD_clear_n : std_logic;
begin
BCD_digit_inst : for i in 1 to 4 generate
char: BCD_digit
port map (
clear_n => BCD_clear_n,
clock => clock,
carry_in => carry_bits(i-1),
carry_out => carry_bits(i),
digit => BCD_counts(4*i-1 downto 4*i-4)
);
end generate;
carry_bits(0) <= BCD_input_reg(15);
scale: process (reset_n, clock)
begin
if reset_n = '0' then
scaled_input <= (others => '0');
elsif clock'event and clock = '1' then
case format_select is
when "001" =>
-- 8V full scale, display volts
-- need to multiply ADC counts x2
scaled_input <= "000" & counts_in & '0';
when "010" =>
-- drop two LSBs to read in deg K then convert to deg C
counts_in_int <= counts_in;
counts_in_int_int <= counts_in_int - "010001101100";
scaled_input <= "000000" & counts_in_int_int(11 downto 2);
when "011" =>
-- divide by 2 (to get mV)
scaled_input <= "00000" & counts_in(11 downto 1) ;
when "100" =>
scaled_input <= "0000" & counts_in ;
when others =>
null;
end case;
end if;
end process;
to_BCD : process (reset_n, clock)
begin
if reset_n = '0' then
BCD_shiftcount <= (others => '0');
BCD_counts_reg <= (others => '0');
BCD_input_reg <= (others => '0');
BCD_clear_n <= '0';
elsif clock'event and clock = '1' then
if BCD_shiftcount = "10000" then
BCD_counts_reg <= BCD_counts; -- latch output
BCD_input_reg <= scaled_input; -- latch new input
BCD_clear_n <= '0';
BCD_shiftcount <= BCD_shiftcount + 1;
elsif BCD_shiftcount = "10001" then
BCD_clear_n <= '1';
BCD_shiftcount <= (others => '0');
else
BCD_input_reg <= BCD_input_reg(14 downto 0) & '0';
BCD_shiftcount <= BCD_shiftcount + 1;
end if;
end if;
end process;
BCD_char4 <= BCD_counts_reg(15 downto 12);
BCD_char3 <= BCD_counts_reg(11 downto 8);
BCD_char2 <= BCD_counts_reg(7 downto 4);
BCD_char1 <= BCD_counts_reg(3 downto 0);
to_display: process (reset_n, clock)
begin
if reset_n = '0' then
data_out <= x"2020202020202020"; -- all spaces
elsif clock'event and clock = '1' then
case format_select is
when "001" =>
-- format is "__n.nnnV"
data_out <= x"2020" &
x"3" & BCD_char4 &
x"2E" &
x"3" & BCD_char3 &
x"3" & BCD_char2 &
x"3" & BCD_char1 &
x"56";
when "010" =>
-- format is "---nnn^C"
data_out <= x"202020" &
x"3" & BCD_char3 &
x"3" & BCD_char2 &
x"3" & BCD_char1 &
x"DF43";
when "011" =>
-- format is "---n.nnV"
data_out <= x"202020" &
x"3" & BCD_char4 &
x"2E" &
x"3" & BCD_char3 &
x"3" & BCD_char2 &
x"56";
when "100" =>
-- format is "---nnnmA"
data_out <= x"202020" &
x"3" & BCD_char3 &
x"3" & BCD_char2 &
x"3" & BCD_char1 &
x"6D41";
when others =>
data_out <= x"20465553494F4E20"; -- Fusion
end case;
end if;
end process;
end behave;
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