seg7led.fit.summary

Verilog HDL源码

Fitter Status : Successful - Fri May 30 15:33:16 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : seg7led
Top-level Entity Name : seg7led
Family : Cyclone III
Device : EP3C25Q240C8
Timing Models : Final
Total logic elements : 95 / 24,624 ( < 1 % )
    Total combinational functions : 95 / 24,624 ( < 1 % )
    Dedicated logic registers : 64 / 24,624 ( < 1 % )
Total registers : 64
Total pins : 14 / 149 ( 9 % )
Total virtual pins : 0
Total memory bits : 0 / 608,256 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )