seg7led.fit.rpt

Verilog HDL源码

; Maximum Core Junction Temperature                                     ; 85                             ;                                       ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                                   ;
; Device I/O Standard                                                   ; 3.3-V LVTTL                    ;                                       ;
; Reserve all unused pins                                               ; As input tri-stated            ; As input tri-stated with weak pull-up ;
; Use smart compilation                                                 ; Off                            ; Off                                   ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                                     ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                                ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                                   ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                                   ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths        ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                                   ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                                  ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation                    ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation                    ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                                    ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                                   ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                         ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                                     ;
; PCI I/O                                                               ; Off                            ; Off                                   ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                                   ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                                   ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                                   ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                                  ;
; Auto Delay Chains                                                     ; On                             ; On                                    ;
; Allow Single-ended Buffer for Differential-XSTL Input                 ; Off                            ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                 ; Off                            ; Off                                   ;
; Auto Merge PLLs                                                       ; On                             ; On                                    ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                                   ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                                   ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                                   ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                              ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                              ; Auto                           ; Auto                                  ;
; Auto Register Duplication                                             ; Auto                           ; Auto                                  ;
; Auto Global Clock                                                     ; On                             ; On                                    ;
; Auto Global Register Control Signals                                  ; On                             ; On                                    ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                                   ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                                   ;
+-----------------------------------------------------------------------+--------------------------------+---------------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in G:/Q71/3C25-V5/seg7led/seg7led.pin.


+---------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                             ;
+---------------------------------------------+-----------------------------+
; Resource                                    ; Usage                       ;
+---------------------------------------------+-----------------------------+
; Total logic elements                        ; 95 / 24,624 ( < 1 % )       ;
;     -- Combinational with no register       ; 31                          ;
;     -- Register only                        ; 0                           ;
;     -- Combinational with a register        ; 64                          ;
;                                             ;                             ;
; Logic element usage by number of LUT inputs ;                             ;
;     -- 4 input functions                    ; 24                          ;
;     -- 3 input functions                    ; 2                           ;
;     -- <=2 input functions                  ; 69                          ;
;     -- Register only                        ; 0                           ;
;                                             ;                             ;
; Logic elements by mode                      ;                             ;
;     -- normal mode                          ; 35                          ;
;     -- arithmetic mode                      ; 60                          ;
;                                             ;                             ;
; Total registers*                            ; 64 / 25,530 ( < 1 % )       ;
;     -- Dedicated logic registers            ; 64 / 24,860 ( < 1 % )       ;
;     -- I/O registers                        ; 0 / 670 ( 0 % )             ;
;                                             ;                             ;
; Total LABs:  partially or completely used   ; 8 / 1,539 ( < 1 % )         ;
; User inserted logic elements                ; 0                           ;
; Virtual pins                                ; 0                           ;
; I/O pins                                    ; 14 / 149 ( 9 % )            ;
;     -- Clock pins                           ; 2 / 8 ( 25 % )              ;
;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )               ;
; Global signals                              ; 2                           ;
; M9Ks                                        ; 0 / 66 ( 0 % )              ;
; Total memory bits                           ; 0 / 608,256 ( 0 % )         ;
; Total RAM block bits                        ; 0 / 608,256 ( 0 % )         ;
; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )             ;
; PLLs                                        ; 0 / 4 ( 0 % )               ;
; Global clocks                               ; 2 / 20 ( 10 % )             ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )               ;
; Average interconnect usage                  ; 0%                          ;
; Peak interconnect usage                     ; 0%                          ;