colorbar.vo

程序实现的功能是在VGA显示器上显示彩色条纹

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "02/09/2007 20:28:23"

// 
// Device: Altera EP2C20F484C8 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	ColorBar (
	rst,
	clk,
	altera_reserved_tms,
	altera_reserved_tck,
	altera_reserved_tdi,
	VGA_HS,
	VGA_VS,
	VGA_BLANK,
	VGA_CLK,
	RGB,
	VGA_RGB,
	altera_reserved_tdo);
input 	rst;
input 	clk;
input 	altera_reserved_tms;
input 	altera_reserved_tck;
input 	altera_reserved_tdi;
output 	VGA_HS;
output 	VGA_VS;
output 	VGA_BLANK;
output 	VGA_CLK;
output 	[12:0] RGB;
output 	[2:0] VGA_RGB;
output 	altera_reserved_tdo;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("ColorBar_v.sdo");
// synopsys translate_on

wire \inst4|altpll_component|_clk1 ;
wire \inst4|altpll_component|_clk2 ;
wire \inst|LessThan~1883 ;
wire \altera_internal_jtag~TCKUTAP ;
wire \inst|vcnt[5] ;
wire \inst|vcnt[0] ;
wire \inst|always4~156 ;
wire \inst|always4~158 ;
wire \inst|vcnt[0]~243 ;
wire \inst|vcnt[5]~253 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[0] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[0] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[1] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[2] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[3] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[1] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~426 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~427 ;
wire \auto_signaltap_0|comb~26 ;
wire \auto_signaltap_0|ela_control|sm2|status_out[0] ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[1] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~249 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|w_anode1w[3] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened_ff[1] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita4 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita6 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita8 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_comb_bita10 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[2] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~428 ;
wire \auto_signaltap_0|crc_rom_sr|reduce_nor~3 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0]~6 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0]~209 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[2]~210 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter~211 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[1]~212 ;
wire \auto_signaltap_0|ela_control|sm1|buffer_write_enable ;
wire \auto_signaltap_0|ela_control|sm2|status_out~111 ;
wire \auto_signaltap_0|ela_control|sm1|ela_done ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|stop_acquisition~100 ;
wire \sld_hub_inst|HUB_INFO_REG|add~78 ;
wire \sld_hub_inst|HUB_INFO_REG|add~83 ;
wire \sld_hub_inst|HUB_INFO_REG|add~84 ;
wire \sld_hub_inst|IRSR_D[2]~407 ;
wire \auto_signaltap_0|acq_trigger_in_reg[0] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff ;
wire \auto_signaltap_0|acq_trigger_in_reg[2] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|holdff ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[3] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~429 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~430 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[7] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[5] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[3] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[1] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|pre_hazard[0] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita0 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita1 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita3 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita5 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_comb_bita7 ;
wire \auto_signaltap_0|ela_control|sm1|edq~70 ;
wire \auto_signaltap_0|ela_control|\trigger_in_trigger_module_enabled_gen:trigger_in_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[4] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~78 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~83 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~431 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~432 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[5] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1317 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_comb_bita6 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_comb_bita8 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_comb_bita9~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_comb_bita10 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[6] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1318 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[7] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1319 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[8] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1320 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[9] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1321 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[10] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1322 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[11] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1323 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[12] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1324 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[13] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[0] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1325 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[14] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|_~1326 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[15] ;