📄 x444_to_422_to_444_poynton.mdl
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explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
mux_type off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Register"
Ports [1, 1]
Position [170, 165, 215, 215]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "0"
reg_only_valid off
explicit_period off
period "1"
rst off
en off
out_en off
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [670, 176, 715, 204]
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "11"
bit1 "0"
base1 "MSB of Input"
bit0 "8"
base0 "LSB of Input"
boolean_output off
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Up Sample"
Ports [1, 1]
Position [455, 167, 500, 213]
FontSize 10
SourceBlock "xbsIndex_r3/Up Sample"
SourceType "Xilinx Up Sampling Block"
sample_ratio "2"
copy_samples on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Up Sample1"
Ports [1, 1]
Position [455, 267, 500, 313]
FontSize 10
SourceBlock "xbsIndex_r3/Up Sample"
SourceType "Xilinx Up Sampling Block"
sample_ratio "2"
copy_samples on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType SubSystem
Name "lookit"
Ports [3]
Position [780, 425, 820, 485]
TreatAsAtomicUnit off
System {
Name "lookit"
Location [214, 82, 1014, 722]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 68, 55, 82]
}
Block {
BlockType Inport
Name "In2"
Position [25, 158, 55, 172]
Port "2"
}
Block {
BlockType Inport
Name "In3"
Position [25, 248, 55, 262]
Port "3"
}
Block {
BlockType Reference
Name "Gateway Out3"
Ports [1, 1]
Position [80, 154, 135, 176]
SourceBlock "xbsIndex_r3/Gateway Out"
SourceType "Xilinx Gateway Out"
hdl_port off
timing_constraint "None"
locs_specified off
LOCs "{}"
needs_fixed_name off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Gateway Out4"
Ports [1, 1]
Position [80, 64, 135, 86]
SourceBlock "xbsIndex_r3/Gateway Out"
SourceType "Xilinx Gateway Out"
hdl_port off
timing_constraint "None"
locs_specified off
LOCs "{}"
needs_fixed_name off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Gateway Out5"
Ports [1, 1]
Position [80, 244, 135, 266]
SourceBlock "xbsIndex_r3/Gateway Out"
SourceType "Xilinx Gateway Out"
hdl_port off
timing_constraint "None"
locs_specified off
LOCs "{}"
needs_fixed_name off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Scope
Name "interpolate"
Ports [3]
Position [215, 27, 260, 303]
Location [5, 60, 1029, 741]
Open off
NumInputPorts "3"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
YMin "-5~-5~-5"
YMax "5~5~5"
SaveName "ScopeData4"
DataFormat "StructureWithTime"
}
Line {
SrcBlock "Gateway Out4"
SrcPort 1
DstBlock "interpolate"
DstPort 1
}
Line {
SrcBlock "Gateway Out3"
SrcPort 1
DstBlock "interpolate"
DstPort 2
}
Line {
SrcBlock "Gateway Out5"
SrcPort 1
DstBlock "interpolate"
DstPort 3
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Gateway Out4"
DstPort 1
}
Line {
SrcBlock "In2"
SrcPort 1
DstBlock "Gateway Out3"
DstPort 1
}
Line {
SrcBlock "In3"
SrcPort 1
DstBlock "Gateway Out5"
DstPort 1
}
}
}
Block {
BlockType Outport
Name "Out1"
Position [830, 183, 860, 197]
}
Line {
SrcBlock "Slice"
SrcPort 1
DstBlock "Convert"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Register"
DstPort 1
}
Line {
SrcBlock "Register"
SrcPort 1
Points [0, 0; 50, 0]
Branch {
DstBlock "FIR"
DstPort 1
}
Branch {
Points [0, 100]
DstBlock "FIR1"
DstPort 1
}
}
Line {
SrcBlock "FIR"
SrcPort 1
DstBlock "Up Sample"
DstPort 1
}
Line {
SrcBlock "FIR1"
SrcPort 1
DstBlock "Up Sample1"
DstPort 1
}
Line {
SrcBlock "Up Sample"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "Mux"
DstPort 2
}
Branch {
Points [0, 265]
DstBlock "lookit"
DstPort 2
}
}
Line {
SrcBlock "Up Sample1"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Mux"
DstPort 3
}
Branch {
Points [0, 185]
DstBlock "lookit"
DstPort 3
}
}
Line {
SrcBlock "Counter"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Slice"
DstPort 1
}
Branch {
Points [0, 245]
DstBlock "lookit"
DstPort 1
}
}
Line {
SrcBlock "Convert"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Poynton\nFilter\nChroma\nInterpolate1"
Ports [1, 1]
Position [80, 250, 120, 310]
TreatAsAtomicUnit off
System {
Name "Poynton\nFilter\nChroma\nInterpolate1"
Location [214, 82, 1014, 722]
Open off
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "93"
Block {
BlockType Inport
Name "In1"
Position [75, 183, 105, 197]
}
Block {
BlockType Reference
Name "Convert"
Ports [1, 1]
Position [760, 175, 805, 205]
SourceBlock "xbsIndex_r3/Convert"
SourceType "Xilinx Converter Block"
arith_type "Unsigned"
n_bits "8"
bin_pt "0"
quantization "Truncate"
overflow "Saturate"
latency "0"
explicit_period off
period "1"
dbl_ovrd off
show_param off
inserted_by_tool off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Counter"
Ports [0, 1]
Position [350, 65, 400, 115]
SourceBlock "xbsIndex_r3/Counter"
SourceType "Xilinx Counter Block"
cnt_type "Free Running"
n_bits "1"
bin_pt "0"
arith_type "Unsigned"
start_count "0"
cnt_to "Inf"
cnt_by_val "1"
operation "Up"
explicit_period off
period "1"
load_pin off
rst off
en off
dbl_ovrd off
show_param off
use_rpm on
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "FIR"
Ports [1, 1]
Position [345, 159, 410, 221]
SourceBlock "xbsIndex_r3/FIR"
SourceType "Xilinx Finite Impulse Response Filter"
coef "[-1 3 -6 12 -24 80 128 80 -24 12 -6 3 -"
"1]"
structure "Inferred from Coefficients"
coef_n_bits "9"
coef_bin_pt "0"
coef_arith_type "Signed (2's complement)"
num_channels "1"
serial_input off
polyphase_behavior "Single Rate: sample in - sample out"
latency "10"
over_sample "9"
explicit_period off
period "1"
reload off
valids off
dbl_ovrd off
show_param off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "FIR1"
Ports [1, 1]
Position [345, 259, 410, 321]
SourceBlock "xbsIndex_r3/FIR"
SourceType "Xilinx Finite Impulse Response Filter"
coef "[2 -3 5 -12 24 112 112 24 -12 5 -3 2]"
structure "Inferred from Coefficients"
coef_n_bits "9"
coef_bin_pt "0"
coef_arith_type "Signed (2's complement)"
num_channels "1"
serial_input off
polyphase_behavior "Single Rate: sample in - sample out"
latency "10"
over_sample "9"
explicit_period off
period "1"
reload off
valids off
dbl_ovrd off
show_param off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Mux"
Ports [3, 1]
Position [565, 38, 630, 342]
FontSize 10
SourceBlock "xbsIndex_r3/Mux"
SourceType "Xilinx Multiplexer Block"
inputs "2"
precision "Full"
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "2"
quantization "Truncate"
overflow "Wrap"
latency "0"
explicit_period off
period "1"
en off
dbl_ovrd off
show_param off
mux_type off
use_rpm off
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Register"
Ports [1, 1]
Position [170, 165, 215, 215]
SourceBlock "xbsIndex_r3/Register"
SourceType "Xilinx Register Block"
init "0"
reg_only_valid off
explicit_period off
period "1"
rst off
en off
out_en off
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [670, 176, 715, 204]
SourceBlock "xbsIndex_r3/Slice"
SourceType "Xilinx Slice Block"
mode "Lower Bit Location + Width"
nbits "11"
bit1 "0"
base1 "MSB of Input"
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